1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2# Copyright 2023 Realtek Semiconductor Corporation 3%YAML 1.2 4--- 5$id: http://devicetree.org/schemas/usb/realtek,rtd-dwc3.yaml# 6$schema: http://devicetree.org/meta-schemas/core.yaml# 7 8title: Realtek DWC3 USB SoC Controller Glue 9 10maintainers: 11 - Stanley Chang <stanley_chang@realtek.com> 12 13description: 14 The Realtek DHC SoC embeds a DWC3 USB IP Core configured for USB 2.0 15 and USB 3.0 in host or dual-role mode. 16 17properties: 18 compatible: 19 items: 20 - enum: 21 - realtek,rtd1295-dwc3 22 - realtek,rtd1315e-dwc3 23 - realtek,rtd1319-dwc3 24 - realtek,rtd1319d-dwc3 25 - realtek,rtd1395-dwc3 26 - realtek,rtd1619-dwc3 27 - realtek,rtd1619b-dwc3 28 - const: realtek,rtd-dwc3 29 30 reg: 31 items: 32 - description: Address and length of register set for wrapper of dwc3 core. 33 - description: Address and length of register set for pm control. 34 35 '#address-cells': 36 const: 1 37 38 '#size-cells': 39 const: 1 40 41 ranges: true 42 43patternProperties: 44 "^usb@[0-9a-f]+$": 45 $ref: snps,dwc3.yaml# 46 description: Required child node 47 48required: 49 - compatible 50 - reg 51 - "#address-cells" 52 - "#size-cells" 53 - ranges 54 55additionalProperties: false 56 57examples: 58 - | 59 usb@98013e00 { 60 compatible = "realtek,rtd1319d-dwc3", "realtek,rtd-dwc3"; 61 reg = <0x98013e00 0x140>, <0x98013f60 0x4>; 62 #address-cells = <1>; 63 #size-cells = <1>; 64 ranges; 65 66 usb@98050000 { 67 compatible = "snps,dwc3"; 68 reg = <0x98050000 0x9000>; 69 interrupts = <0 94 4>; 70 phys = <&usb2phy &usb3phy>; 71 phy-names = "usb2-phy", "usb3-phy"; 72 dr_mode = "otg"; 73 usb-role-switch; 74 role-switch-default-mode = "host"; 75 snps,dis_u2_susphy_quirk; 76 snps,parkmode-disable-ss-quirk; 77 snps,parkmode-disable-hs-quirk; 78 maximum-speed = "high-speed"; 79 }; 80 }; 81