1MediaTek musb DRD/OTG controller 2------------------------------------------- 3 4Required properties: 5 - compatible : should be one of: 6 "mediatek,mt2701-musb" 7 ... 8 followed by "mediatek,mtk-musb" 9 - reg : specifies physical base address and size of 10 the registers 11 - interrupts : interrupt used by musb controller 12 - interrupt-names : must be "mc" 13 - phys : PHY specifier for the OTG phy 14 - dr_mode : should be one of "host", "peripheral" or "otg", 15 refer to usb/generic.txt 16 - clocks : a list of phandle + clock-specifier pairs, one for 17 each entry in clock-names 18 - clock-names : must contain "main", "mcu", "univpll" 19 for clocks of controller 20 21Optional properties: 22 - power-domains : a phandle to USB power domain node to control USB's 23 MTCMOS 24 25Required child nodes: 26 usb connector node as defined in bindings/connector/usb-connector.yaml 27Optional properties: 28 - id-gpios : input GPIO for USB ID pin. 29 - vbus-gpios : input GPIO for USB VBUS pin. 30 - vbus-supply : reference to the VBUS regulator, needed when supports 31 dual-role mode 32 - usb-role-switch : use USB Role Switch to support dual-role switch, see 33 usb/generic.txt. 34 35Example: 36 37usb2: usb@11200000 { 38 compatible = "mediatek,mt2701-musb", 39 "mediatek,mtk-musb"; 40 reg = <0 0x11200000 0 0x1000>; 41 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_LOW>; 42 interrupt-names = "mc"; 43 phys = <&u2port2 PHY_TYPE_USB2>; 44 dr_mode = "otg"; 45 clocks = <&pericfg CLK_PERI_USB0>, 46 <&pericfg CLK_PERI_USB0_MCU>, 47 <&pericfg CLK_PERI_USB_SLV>; 48 clock-names = "main","mcu","univpll"; 49 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; 50 usb-role-switch; 51 connector{ 52 compatible = "gpio-usb-b-connector", "usb-b-connector"; 53 type = "micro"; 54 id-gpios = <&pio 44 GPIO_ACTIVE_HIGH>; 55 vbus-supply = <&usb_vbus>; 56 }; 57}; 58