1HiSilicon STB xHCI 2 3The device node for HiSilicon STB xHCI host controller 4 5Required properties: 6 - compatible: should be "hisilicon,hi3798cv200-xhci" 7 - reg: specifies physical base address and size of the registers 8 - interrupts : interrupt used by the controller 9 - clocks: a list of phandle + clock-specifier pairs, one for each 10 entry in clock-names 11 - clock-names: must contain 12 "bus": for bus clock 13 "utmi": for utmi clock 14 "pipe": for pipe clock 15 "suspend": for suspend clock 16 - resets: a list of phandle and reset specifier pairs as listed in 17 reset-names property. 18 - reset-names: must contain 19 "soft": for soft reset 20 - phys: a list of phandle + phy specifier pairs 21 - phy-names: must contain at least one of following: 22 "inno": for inno phy 23 "combo": for combo phy 24 25Optional properties: 26 - usb2-lpm-disable: indicate if we don't want to enable USB2 HW LPM 27 - usb3-lpm-capable: determines if platform is USB3 LPM capable 28 - imod-interval-ns: default interrupt moderation interval is 40000ns 29 30Example: 31 32xhci0: xchi@f98a0000 { 33 compatible = "hisilicon,hi3798cv200-xhci"; 34 reg = <0xf98a0000 0x10000>; 35 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 36 clocks = <&crg HISTB_USB3_BUS_CLK>, 37 <&crg HISTB_USB3_UTMI_CLK>, 38 <&crg HISTB_USB3_PIPE_CLK>, 39 <&crg HISTB_USB3_SUSPEND_CLK>; 40 clock-names = "bus", "utmi", "pipe", "suspend"; 41 resets = <&crg 0xb0 12>; 42 reset-names = "soft"; 43 phys = <&usb2_phy1_port1 0>, <&combphy0 PHY_TYPE_USB3>; 44 phy-names = "inno", "combo"; 45}; 46