1Xilinx SuperSpeed DWC3 USB SoC controller 2 3Required properties: 4- compatible: Should contain "xlnx,zynqmp-dwc3" 5- clocks: A list of phandles for the clocks listed in clock-names 6- clock-names: Should contain the following: 7 "bus_clk" Master/Core clock, have to be >= 125 MHz for SS 8 operation and >= 60MHz for HS operation 9 10 "ref_clk" Clock source to core during PHY power down 11 12Required child node: 13A child node must exist to represent the core DWC3 IP block. The name of 14the node is not important. The content of the node is defined in dwc3.txt. 15 16Example device node: 17 18 usb@0 { 19 #address-cells = <0x2>; 20 #size-cells = <0x1>; 21 compatible = "xlnx,zynqmp-dwc3"; 22 clock-names = "bus_clk" "ref_clk"; 23 clocks = <&clk125>, <&clk125>; 24 ranges; 25 26 dwc3@fe200000 { 27 compatible = "snps,dwc3"; 28 reg = <0x0 0xfe200000 0x40000>; 29 interrupts = <0x0 0x41 0x4>; 30 dr_mode = "host"; 31 }; 32 }; 33