1Cavium SuperSpeed DWC3 USB SoC controller 2 3Required properties: 4- compatible: Should contain "cavium,octeon-7130-usb-uctl" 5 6Required child node: 7A child node must exist to represent the core DWC3 IP block. The name of 8the node is not important. The content of the node is defined in dwc3.txt. 9 10Example device node: 11 12 uctl@1180069000000 { 13 compatible = "cavium,octeon-7130-usb-uctl"; 14 reg = <0x00011800 0x69000000 0x00000000 0x00000100>; 15 ranges; 16 #address-cells = <0x00000002>; 17 #size-cells = <0x00000002>; 18 refclk-frequency = <0x05f5e100>; 19 refclk-type-ss = "dlmc_ref_clk0"; 20 refclk-type-hs = "dlmc_ref_clk0"; 21 power = <0x00000002 0x00000002 0x00000001>; 22 xhci@1690000000000 { 23 compatible = "cavium,octeon-7130-xhci", "snps,dwc3"; 24 reg = <0x00016900 0x00000000 0x00000010 0x00000000>; 25 interrupt-parent = <0x00000010>; 26 interrupts = <0x00000009 0x00000004>; 27 }; 28 }; 29