1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/usb/ci-hdrc-usb2.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: USB2 ChipIdea USB controller 8 9maintainers: 10 - Xu Yang <xu.yang_2@nxp.com> 11 - Peng Fan <peng.fan@nxp.com> 12 13properties: 14 compatible: 15 oneOf: 16 - enum: 17 - chipidea,usb2 18 - lsi,zevio-usb 19 - nvidia,tegra20-ehci 20 - nvidia,tegra20-udc 21 - nvidia,tegra30-ehci 22 - nvidia,tegra30-udc 23 - nvidia,tegra114-udc 24 - nvidia,tegra124-udc 25 - qcom,ci-hdrc 26 - items: 27 - enum: 28 - nvidia,tegra114-ehci 29 - nvidia,tegra124-ehci 30 - nvidia,tegra210-ehci 31 - const: nvidia,tegra30-ehci 32 - items: 33 - enum: 34 - fsl,imx23-usb 35 - fsl,imx25-usb 36 - fsl,imx28-usb 37 - fsl,imx50-usb 38 - fsl,imx51-usb 39 - fsl,imx53-usb 40 - fsl,imx6q-usb 41 - fsl,imx6sl-usb 42 - fsl,imx6sx-usb 43 - fsl,imx6ul-usb 44 - fsl,imx7d-usb 45 - fsl,vf610-usb 46 - const: fsl,imx27-usb 47 - items: 48 - const: fsl,imx8dxl-usb 49 - const: fsl,imx7ulp-usb 50 - const: fsl,imx6ul-usb 51 - items: 52 - enum: 53 - fsl,imx8mm-usb 54 - fsl,imx8mn-usb 55 - const: fsl,imx7d-usb 56 - const: fsl,imx27-usb 57 - items: 58 - enum: 59 - fsl,imx6sll-usb 60 - fsl,imx7ulp-usb 61 - const: fsl,imx6ul-usb 62 - const: fsl,imx27-usb 63 - items: 64 - const: xlnx,zynq-usb-2.20a 65 - const: chipidea,usb2 66 67 reg: 68 minItems: 1 69 maxItems: 2 70 71 interrupts: 72 minItems: 1 73 maxItems: 2 74 75 clocks: 76 minItems: 1 77 maxItems: 2 78 79 clock-names: 80 minItems: 1 81 maxItems: 2 82 83 dr_mode: true 84 85 power-domains: 86 maxItems: 1 87 88 resets: 89 maxItems: 1 90 91 reset-names: 92 maxItems: 1 93 94 "#reset-cells": 95 const: 1 96 97 phy_type: true 98 99 itc-setting: 100 description: 101 interrupt threshold control register control, the setting should be 102 aligned with ITC bits at register USBCMD. 103 $ref: /schemas/types.yaml#/definitions/uint32 104 105 ahb-burst-config: 106 description: 107 it is vendor dependent, the required value should be aligned with 108 AHBBRST at SBUSCFG, the range is from 0x0 to 0x7. This property is 109 used to change AHB burst configuration, check the chipidea spec for 110 meaning of each value. If this property is not existed, it will use 111 the reset value. 112 $ref: /schemas/types.yaml#/definitions/uint32 113 minimum: 0x0 114 maximum: 0x7 115 116 tx-burst-size-dword: 117 description: 118 it is vendor dependent, the tx burst size in dword (4 bytes), This 119 register represents the maximum length of a the burst in 32-bit 120 words while moving data from system memory to the USB bus, the value 121 of this property will only take effect if property "ahb-burst-config" 122 is set to 0, if this property is missing the reset default of the 123 hardware implementation will be used. 124 $ref: /schemas/types.yaml#/definitions/uint32 125 minimum: 0x0 126 maximum: 0x20 127 128 rx-burst-size-dword: 129 description: 130 it is vendor dependent, the rx burst size in dword (4 bytes), This 131 register represents the maximum length of a the burst in 32-bit words 132 while moving data from the USB bus to system memory, the value of 133 this property will only take effect if property "ahb-burst-config" 134 is set to 0, if this property is missing the reset default of the 135 hardware implementation will be used. 136 $ref: /schemas/types.yaml#/definitions/uint32 137 minimum: 0x0 138 maximum: 0x20 139 140 extcon: 141 description: 142 Phandles to external connector devices. First phandle should point 143 to external connector, which provide "USB" cable events, the second 144 should point to external connector device, which provide "USB-HOST" 145 cable events. If one of the external connector devices is not 146 required, empty <0> phandle should be specified. 147 $ref: /schemas/types.yaml#/definitions/phandle-array 148 minItems: 1 149 items: 150 - description: vbus extcon 151 - description: id extcon 152 153 phy-clkgate-delay-us: 154 description: 155 The delay time (us) between putting the PHY into low power mode and 156 gating the PHY clock. 157 158 non-zero-ttctrl-ttha: 159 description: 160 After setting this property, the value of register ttctrl.ttha 161 will be 0x7f; if not, the value will be 0x0, this is the default 162 value. It needs to be very carefully for setting this property, it 163 is recommended that consult with your IC engineer before setting 164 this value. On the most of chipidea platforms, the "usage_tt" flag 165 at RTL is 0, so this property only affects siTD. 166 167 If this property is not set, the max packet size is 1023 bytes, and 168 if the total of packet size for pervious transactions are more than 169 256 bytes, it can't accept any transactions within this frame. The 170 use case is single transaction, but higher frame rate. 171 172 If this property is set, the max packet size is 188 bytes, it can 173 handle more transactions than above case, it can accept transactions 174 until it considers the left room size within frame is less than 188 175 bytes, software needs to make sure it does not send more than 90% 176 maximum_periodic_data_per_frame. The use case is multiple 177 transactions, but less frame rate. 178 type: boolean 179 180 mux-controls: 181 description: 182 The mux control for toggling host/device output of this controller. 183 It's expected that a mux state of 0 indicates device mode and a mux 184 state of 1 indicates host mode. 185 maxItems: 1 186 187 mux-control-names: 188 const: usb_switch 189 190 operating-points-v2: 191 description: A phandle to the OPP table containing the performance states. 192 $ref: /schemas/types.yaml#/definitions/phandle 193 194 pinctrl-names: 195 description: 196 Names for optional pin modes in "default", "host", "device". 197 In case of HSIC-mode, "idle" and "active" pin modes are mandatory. 198 In this case, the "idle" state needs to pull down the data and 199 strobe pin and the "active" state needs to pull up the strobe pin. 200 oneOf: 201 - items: 202 - const: idle 203 - const: active 204 - items: 205 - const: default 206 - enum: 207 - host 208 - device 209 - items: 210 - const: default 211 212 pinctrl-0: 213 maxItems: 1 214 215 pinctrl-1: 216 maxItems: 1 217 218 phys: 219 maxItems: 1 220 221 phy-names: 222 const: usb-phy 223 224 phy-select: 225 description: 226 Phandler of TCSR node with two argument that indicate register 227 offset, and phy index 228 $ref: /schemas/types.yaml#/definitions/phandle-array 229 items: 230 - description: phandle to TCSR node 231 - description: register offset 232 - description: phy index 233 234 vbus-supply: 235 description: reference to the VBUS regulator. 236 237 fsl,usbmisc: 238 description: 239 Phandler of non-core register device, with one argument that 240 indicate usb controller index 241 $ref: /schemas/types.yaml#/definitions/phandle-array 242 items: 243 - items: 244 - description: phandle to usbmisc node 245 - description: index of usb controller 246 247 fsl,anatop: 248 description: phandle for the anatop node. 249 $ref: /schemas/types.yaml#/definitions/phandle 250 251 disable-over-current: 252 type: boolean 253 description: disable over current detect 254 255 over-current-active-low: 256 type: boolean 257 description: over current signal polarity is active low 258 259 over-current-active-high: 260 type: boolean 261 description: 262 Over current signal polarity is active high. It's recommended to 263 specify the over current polarity. 264 265 power-active-high: 266 type: boolean 267 description: power signal polarity is active high 268 269 external-vbus-divider: 270 type: boolean 271 description: enables off-chip resistor divider for Vbus 272 273 samsung,picophy-pre-emp-curr-control: 274 description: 275 HS Transmitter Pre-Emphasis Current Control. This signal controls 276 the amount of current sourced to the USB_OTG*_DP and USB_OTG*_DN 277 pins after a J-to-K or K-to-J transition. The range is from 0x0 to 278 0x3, the default value is 0x1. Details can refer to TXPREEMPAMPTUNE0 279 bits of USBNC_n_PHY_CFG1. 280 $ref: /schemas/types.yaml#/definitions/uint32 281 minimum: 0x0 282 maximum: 0x3 283 284 samsung,picophy-dc-vol-level-adjust: 285 description: 286 HS DC Voltage Level Adjustment. Adjust the high-speed transmitter DC 287 level voltage. The range is from 0x0 to 0xf, the default value is 288 0x3. Details can refer to TXVREFTUNE0 bits of USBNC_n_PHY_CFG1. 289 $ref: /schemas/types.yaml#/definitions/uint32 290 minimum: 0x0 291 maximum: 0xf 292 293 usb-phy: 294 description: phandle for the PHY device. Use "phys" instead. 295 $ref: /schemas/types.yaml#/definitions/phandle 296 deprecated: true 297 298 fsl,usbphy: 299 description: phandle of usb phy that connects to the port. Use "phys" instead. 300 $ref: /schemas/types.yaml#/definitions/phandle 301 deprecated: true 302 303 nvidia,phy: 304 description: phandle of usb phy that connects to the port. Use "phys" instead. 305 $ref: /schemas/types.yaml#/definitions/phandle 306 deprecated: true 307 308 nvidia,needs-double-reset: 309 description: Indicates double reset or not. 310 type: boolean 311 deprecated: true 312 313 port: 314 description: 315 Any connector to the data bus of this controller should be modelled 316 using the OF graph bindings specified, if the "usb-role-switch" 317 property is used. 318 $ref: /schemas/graph.yaml#/properties/port 319 320 reset-gpios: 321 maxItems: 1 322 323 ulpi: 324 type: object 325 additionalProperties: false 326 patternProperties: 327 "^phy(-[0-9])?$": 328 description: The phy child node for Qcom chips. 329 type: object 330 $ref: /schemas/phy/qcom,usb-hs-phy.yaml 331 332dependencies: 333 port: [ usb-role-switch ] 334 mux-controls: [ mux-control-names ] 335 336required: 337 - compatible 338 - reg 339 - interrupts 340 341allOf: 342 - $ref: usb-hcd.yaml# 343 - $ref: usb-drd.yaml# 344 - if: 345 properties: 346 phy_type: 347 const: hsic 348 required: 349 - phy_type 350 then: 351 properties: 352 pinctrl-names: 353 items: 354 - const: idle 355 - const: active 356 else: 357 properties: 358 pinctrl-names: 359 minItems: 1 360 maxItems: 2 361 oneOf: 362 - items: 363 - const: default 364 - enum: 365 - host 366 - device 367 - items: 368 - const: default 369 - if: 370 properties: 371 compatible: 372 contains: 373 enum: 374 - chipidea,usb2 375 - lsi,zevio-usb 376 - nvidia,tegra20-udc 377 - nvidia,tegra30-udc 378 - nvidia,tegra114-udc 379 - nvidia,tegra124-udc 380 - qcom,ci-hdrc 381 - xlnx,zynq-usb-2.20a 382 then: 383 properties: 384 fsl,usbmisc: false 385 disable-over-current: false 386 over-current-active-low: false 387 over-current-active-high: false 388 power-active-high: false 389 external-vbus-divider: false 390 samsung,picophy-pre-emp-curr-control: false 391 samsung,picophy-dc-vol-level-adjust: false 392 393unevaluatedProperties: false 394 395examples: 396 - | 397 #include <dt-bindings/interrupt-controller/arm-gic.h> 398 #include <dt-bindings/clock/berlin2.h> 399 400 usb@f7ed0000 { 401 compatible = "chipidea,usb2"; 402 reg = <0xf7ed0000 0x10000>; 403 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 404 clocks = <&chip CLKID_USB0>; 405 phys = <&usb_phy0>; 406 phy-names = "usb-phy"; 407 vbus-supply = <®_usb0_vbus>; 408 itc-setting = <0x4>; /* 4 micro-frames */ 409 /* Incremental burst of unspecified length */ 410 ahb-burst-config = <0x0>; 411 tx-burst-size-dword = <0x10>; /* 64 bytes */ 412 rx-burst-size-dword = <0x10>; 413 extcon = <0>, <&usb_id>; 414 phy-clkgate-delay-us = <400>; 415 mux-controls = <&usb_switch>; 416 mux-control-names = "usb_switch"; 417 }; 418 419 # Example for HSIC: 420 - | 421 #include <dt-bindings/interrupt-controller/arm-gic.h> 422 #include <dt-bindings/clock/imx6qdl-clock.h> 423 424 usb@2184400 { 425 compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; 426 reg = <0x02184400 0x200>; 427 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>; 428 clocks = <&clks IMX6QDL_CLK_USBOH3>; 429 fsl,usbphy = <&usbphynop1>; 430 fsl,usbmisc = <&usbmisc 2>; 431 phy_type = "hsic"; 432 dr_mode = "host"; 433 ahb-burst-config = <0x0>; 434 tx-burst-size-dword = <0x10>; 435 rx-burst-size-dword = <0x10>; 436 pinctrl-names = "idle", "active"; 437 pinctrl-0 = <&pinctrl_usbh2_idle>; 438 pinctrl-1 = <&pinctrl_usbh2_active>; 439 #address-cells = <1>; 440 #size-cells = <0>; 441 442 ethernet@1 { 443 compatible = "usb424,9730"; 444 reg = <1>; 445 }; 446 }; 447 448... 449