1* Universal Flash Storage (UFS) Host Controller 2 3UFSHC nodes are defined to describe on-chip UFS host controllers. 4Each UFS controller instance should have its own node. 5 6Required properties: 7- compatible : must contain "jedec,ufs-1.1" or "jedec,ufs-2.0" 8 9 For Qualcomm SoCs must contain, as below, an 10 SoC-specific compatible along with "qcom,ufshc" and 11 the appropriate jedec string: 12 "qcom,msm8994-ufshc", "qcom,ufshc", "jedec,ufs-2.0" 13 "qcom,msm8996-ufshc", "qcom,ufshc", "jedec,ufs-2.0" 14 "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0" 15 "qcom,sdm845-ufshc", "qcom,ufshc", "jedec,ufs-2.0" 16 "qcom,sm8150-ufshc", "qcom,ufshc", "jedec,ufs-2.0" 17 "qcom,sm8250-ufshc", "qcom,ufshc", "jedec,ufs-2.0" 18 "qcom,sm8350-ufshc", "qcom,ufshc", "jedec,ufs-2.0" 19- interrupts : <interrupt mapping for UFS host controller IRQ> 20- reg : <registers mapping> 21 22Optional properties: 23- phys : phandle to UFS PHY node 24- phy-names : the string "ufsphy" when is found in a node, along 25 with "phys" attribute, provides phandle to UFS PHY node 26- vdd-hba-supply : phandle to UFS host controller supply regulator node 27- vcc-supply : phandle to VCC supply regulator node 28- vccq-supply : phandle to VCCQ supply regulator node 29- vccq2-supply : phandle to VCCQ2 supply regulator node 30- vcc-supply-1p8 : For embedded UFS devices, valid VCC range is 1.7-1.95V 31 or 2.7-3.6V. This boolean property when set, specifies 32 to use low voltage range of 1.7-1.95V. Note for external 33 UFS cards this property is invalid and valid VCC range is 34 always 2.7-3.6V. 35- vcc-max-microamp : specifies max. load that can be drawn from vcc supply 36- vccq-max-microamp : specifies max. load that can be drawn from vccq supply 37- vccq2-max-microamp : specifies max. load that can be drawn from vccq2 supply 38 39- clocks : List of phandle and clock specifier pairs 40- clock-names : List of clock input name strings sorted in the same 41 order as the clocks property. 42 "ref_clk" indicates reference clock frequency. 43 UFS host supplies reference clock to UFS device and UFS device 44 specification allows host to provide one of the 4 frequencies (19.2 MHz, 45 26 MHz, 38.4 MHz, 52MHz) for reference clock. This "ref_clk" entry is 46 parsed and used to update the reference clock setting in device. 47 Defaults to 26 MHz(as per specification) if not specified by host. 48- freq-table-hz : Array of <min max> operating frequencies stored in the same 49 order as the clocks property. If this property is not 50 defined or a value in the array is "0" then it is assumed 51 that the frequency is set by the parent clock or a 52 fixed rate clock source. 53-lanes-per-direction : number of lanes available per direction - either 1 or 2. 54 Note that it is assume same number of lanes is used both 55 directions at once. If not specified, default is 2 lanes per direction. 56- #reset-cells : Must be <1> for Qualcomm UFS controllers that expose 57 PHY reset from the UFS controller. 58- resets : reset node register 59- reset-names : describe reset node register, the "rst" corresponds to reset the whole UFS IP. 60- reset-gpios : A phandle and gpio specifier denoting the GPIO connected 61 to the RESET pin of the UFS memory device. 62 63Note: If above properties are not defined it can be assumed that the supply 64regulators or clocks are always on. 65 66Example: 67 ufshc@fc598000 { 68 compatible = "jedec,ufs-1.1"; 69 reg = <0xfc598000 0x800>; 70 interrupts = <0 28 0>; 71 72 vdd-hba-supply = <&xxx_reg0>; 73 vcc-supply = <&xxx_reg1>; 74 vcc-supply-1p8; 75 vccq-supply = <&xxx_reg2>; 76 vccq2-supply = <&xxx_reg3>; 77 vcc-max-microamp = 500000; 78 vccq-max-microamp = 200000; 79 vccq2-max-microamp = 200000; 80 81 clocks = <&core 0>, <&ref 0>, <&phy 0>, <&iface 0>; 82 clock-names = "core_clk", "ref_clk", "phy_clk", "iface_clk"; 83 freq-table-hz = <100000000 200000000>, <0 0>, <0 0>, <0 0>; 84 resets = <&reset 0 1>; 85 reset-names = "rst"; 86 phys = <&ufsphy1>; 87 phy-names = "ufsphy"; 88 #reset-cells = <1>; 89 }; 90