1* Hisilicon Universal Flash Storage (UFS) Host Controller 2 3UFS nodes are defined to describe on-chip UFS hardware macro. 4Each UFS Host Controller should have its own node. 5 6Required properties: 7- compatible : compatible list, contains one of the following - 8 "hisilicon,hi3660-ufs", "jedec,ufs-1.1" for hisi ufs 9 host controller present on Hi3660 chipset. 10 "hisilicon,hi3670-ufs", "jedec,ufs-2.1" for hisi ufs 11 host controller present on Hi3670 chipset. 12- reg : should contain UFS register address space & UFS SYS CTRL register address, 13- interrupts : interrupt number 14- clocks : List of phandle and clock specifier pairs 15- clock-names : List of clock input name strings sorted in the same 16 order as the clocks property. "ref_clk", "phy_clk" is optional 17- freq-table-hz : Array of <min max> operating frequencies stored in the same 18 order as the clocks property. If this property is not 19 defined or a value in the array is "0" then it is assumed 20 that the frequency is set by the parent clock or a 21 fixed rate clock source. 22- resets : describe reset node register 23- reset-names : reset node register, the "rst" corresponds to reset the whole UFS IP. 24 25Example: 26 27 ufs: ufs@ff3b0000 { 28 compatible = "hisilicon,hi3660-ufs", "jedec,ufs-1.1"; 29 /* 0: HCI standard */ 30 /* 1: UFS SYS CTRL */ 31 reg = <0x0 0xff3b0000 0x0 0x1000>, 32 <0x0 0xff3b1000 0x0 0x1000>; 33 interrupt-parent = <&gic>; 34 interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>; 35 clocks = <&crg_ctrl HI3660_CLK_GATE_UFSIO_REF>, 36 <&crg_ctrl HI3660_CLK_GATE_UFSPHY_CFG>; 37 clock-names = "ref_clk", "phy_clk"; 38 freq-table-hz = <0 0>, <0 0>; 39 /* offset: 0x84; bit: 12 */ 40 resets = <&crg_rst 0x84 12>; 41 reset-names = "rst"; 42 }; 43