xref: /freebsd/sys/contrib/device-tree/Bindings/ufs/samsung,exynos-ufs.yaml (revision 3a3af6b2a160bea72509a9d5ef84e25906b0478a) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/ufs/samsung,exynos-ufs.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Samsung SoC series UFS host controller Device Tree Bindings
8
9maintainers:
10  - Alim Akhtar <alim.akhtar@samsung.com>
11
12description: |
13  Each Samsung UFS host controller instance should have its own node.
14
15allOf:
16  - $ref: ufs-common.yaml
17
18properties:
19  compatible:
20    enum:
21      - samsung,exynos7-ufs
22      - samsung,exynosautov9-ufs
23      - samsung,exynosautov9-ufs-vh
24
25  reg:
26    items:
27      - description: HCI register
28      - description: vendor specific register
29      - description: unipro register
30      - description: UFS protector register
31
32  reg-names:
33    items:
34      - const: hci
35      - const: vs_hci
36      - const: unipro
37      - const: ufsp
38
39  clocks:
40    items:
41      - description: ufs link core clock
42      - description: unipro main clock
43
44  clock-names:
45    items:
46      - const: core_clk
47      - const: sclk_unipro_main
48
49  phys:
50    maxItems: 1
51
52  phy-names:
53    const: ufs-phy
54
55  samsung,sysreg:
56    $ref: '/schemas/types.yaml#/definitions/phandle-array'
57    description: Should be phandle/offset pair. The phandle to the syscon node
58                 which indicates the FSYSx sysreg interface and the offset of
59                 the control register for UFS io coherency setting.
60
61  dma-coherent: true
62
63required:
64  - compatible
65  - reg
66  - phys
67  - phy-names
68  - clocks
69  - clock-names
70
71unevaluatedProperties: false
72
73examples:
74  - |
75    #include <dt-bindings/interrupt-controller/arm-gic.h>
76    #include <dt-bindings/clock/exynos7-clk.h>
77
78    ufs: ufs@15570000 {
79       compatible = "samsung,exynos7-ufs";
80       reg = <0x15570000 0x100>,
81             <0x15570100 0x100>,
82             <0x15571000 0x200>,
83             <0x15572000 0x300>;
84       reg-names = "hci", "vs_hci", "unipro", "ufsp";
85       interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
86       clocks = <&clock_fsys1 ACLK_UFS20_LINK>,
87                <&clock_fsys1 SCLK_UFSUNIPRO20_USER>;
88       clock-names = "core_clk", "sclk_unipro_main";
89       pinctrl-names = "default";
90       pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>;
91       phys = <&ufs_phy>;
92       phy-names = "ufs-phy";
93    };
94...
95