xref: /freebsd/sys/contrib/device-tree/Bindings/ufs/qcom,ufs.yaml (revision e6bfd18d21b225af6a0ed67ceeaf1293b7b9eba5) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/ufs/qcom,ufs.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Universal Flash Storage (UFS) Controller
8
9maintainers:
10  - Bjorn Andersson <bjorn.andersson@linaro.org>
11  - Andy Gross <agross@kernel.org>
12
13# Select only our matches, not all jedec,ufs-2.0
14select:
15  properties:
16    compatible:
17      contains:
18        const: qcom,ufshc
19  required:
20    - compatible
21
22properties:
23  compatible:
24    items:
25      - enum:
26          - qcom,msm8994-ufshc
27          - qcom,msm8996-ufshc
28          - qcom,msm8998-ufshc
29          - qcom,sc8280xp-ufshc
30          - qcom,sdm845-ufshc
31          - qcom,sm6350-ufshc
32          - qcom,sm8150-ufshc
33          - qcom,sm8250-ufshc
34          - qcom,sm8350-ufshc
35          - qcom,sm8450-ufshc
36      - const: qcom,ufshc
37      - const: jedec,ufs-2.0
38
39  clocks:
40    minItems: 8
41    maxItems: 11
42
43  clock-names:
44    minItems: 8
45    maxItems: 11
46
47  interconnects:
48    minItems: 2
49    maxItems: 2
50
51  interconnect-names:
52    items:
53      - const: ufs-ddr
54      - const: cpu-ufs
55
56  iommus:
57    minItems: 1
58    maxItems: 2
59
60  phys:
61    maxItems: 1
62
63  phy-names:
64    items:
65      - const: ufsphy
66
67  power-domains:
68    maxItems: 1
69
70  reg:
71    minItems: 1
72    maxItems: 2
73
74  resets:
75    maxItems: 1
76
77  '#reset-cells':
78    const: 1
79
80  reset-names:
81    items:
82      - const: rst
83
84  reset-gpios:
85    maxItems: 1
86    description:
87      GPIO connected to the RESET pin of the UFS memory device.
88
89required:
90  - compatible
91  - reg
92
93allOf:
94  - $ref: ufs-common.yaml
95
96  - if:
97      properties:
98        compatible:
99          contains:
100            enum:
101              - qcom,msm8998-ufshc
102              - qcom,sc8280xp-ufshc
103              - qcom,sm8250-ufshc
104              - qcom,sm8350-ufshc
105              - qcom,sm8450-ufshc
106    then:
107      properties:
108        clocks:
109          minItems: 8
110          maxItems: 8
111        clock-names:
112          items:
113            - const: core_clk
114            - const: bus_aggr_clk
115            - const: iface_clk
116            - const: core_clk_unipro
117            - const: ref_clk
118            - const: tx_lane0_sync_clk
119            - const: rx_lane0_sync_clk
120            - const: rx_lane1_sync_clk
121        reg:
122          minItems: 1
123          maxItems: 1
124
125  - if:
126      properties:
127        compatible:
128          contains:
129            enum:
130              - qcom,sdm845-ufshc
131              - qcom,sm6350-ufshc
132              - qcom,sm8150-ufshc
133    then:
134      properties:
135        clocks:
136          minItems: 9
137          maxItems: 9
138        clock-names:
139          items:
140            - const: core_clk
141            - const: bus_aggr_clk
142            - const: iface_clk
143            - const: core_clk_unipro
144            - const: ref_clk
145            - const: tx_lane0_sync_clk
146            - const: rx_lane0_sync_clk
147            - const: rx_lane1_sync_clk
148            - const: ice_core_clk
149        reg:
150          minItems: 2
151          maxItems: 2
152
153  - if:
154      properties:
155        compatible:
156          contains:
157            enum:
158              - qcom,msm8996-ufshc
159    then:
160      properties:
161        clocks:
162          minItems: 11
163          maxItems: 11
164        clock-names:
165          items:
166            - const: core_clk_src
167            - const: core_clk
168            - const: bus_clk
169            - const: bus_aggr_clk
170            - const: iface_clk
171            - const: core_clk_unipro_src
172            - const: core_clk_unipro
173            - const: core_clk_ice
174            - const: ref_clk
175            - const: tx_lane0_sync_clk
176            - const: rx_lane0_sync_clk
177        reg:
178          minItems: 1
179          maxItems: 1
180
181    # TODO: define clock bindings for qcom,msm8994-ufshc
182
183unevaluatedProperties: false
184
185examples:
186  - |
187    #include <dt-bindings/clock/qcom,gcc-sm8450.h>
188    #include <dt-bindings/clock/qcom,rpmh.h>
189    #include <dt-bindings/gpio/gpio.h>
190    #include <dt-bindings/interconnect/qcom,sm8450.h>
191    #include <dt-bindings/interrupt-controller/arm-gic.h>
192
193    soc {
194        #address-cells = <2>;
195        #size-cells = <2>;
196
197        ufs@1d84000 {
198            compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
199                         "jedec,ufs-2.0";
200            reg = <0 0x01d84000 0 0x3000>;
201            interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
202            phys = <&ufs_mem_phy_lanes>;
203            phy-names = "ufsphy";
204            lanes-per-direction = <2>;
205            #reset-cells = <1>;
206            resets = <&gcc GCC_UFS_PHY_BCR>;
207            reset-names = "rst";
208            reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;
209
210            vcc-supply = <&vreg_l7b_2p5>;
211            vcc-max-microamp = <1100000>;
212            vccq-supply = <&vreg_l9b_1p2>;
213            vccq-max-microamp = <1200000>;
214
215            power-domains = <&gcc UFS_PHY_GDSC>;
216            iommus = <&apps_smmu 0xe0 0x0>;
217            interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>,
218                            <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>;
219            interconnect-names = "ufs-ddr", "cpu-ufs";
220
221            clock-names = "core_clk",
222                          "bus_aggr_clk",
223                          "iface_clk",
224                          "core_clk_unipro",
225                          "ref_clk",
226                          "tx_lane0_sync_clk",
227                          "rx_lane0_sync_clk",
228                          "rx_lane1_sync_clk";
229            clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
230                     <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
231                     <&gcc GCC_UFS_PHY_AHB_CLK>,
232                     <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
233                     <&rpmhcc RPMH_CXO_CLK>,
234                     <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
235                     <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
236                     <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
237            freq-table-hz = <75000000 300000000>,
238                            <0 0>,
239                            <0 0>,
240                            <75000000 300000000>,
241                            <75000000 300000000>,
242                            <0 0>,
243                            <0 0>,
244                            <0 0>;
245        };
246    };
247