xref: /freebsd/sys/contrib/device-tree/Bindings/tpm/google,cr50.yaml (revision 8d13bc63c0e1d50bc9e47ac1f26329c999bfecf0)

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/tpm/google,cr50.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Google Security Chip H1 (running Cr50 firmware)

maintainers:
  - Andrey Pronin <apronin@chromium.org>

description: |
  Google has designed a family of security chips called "Titan".
  One member is the H1 built into Chromebooks and running Cr50 firmware:
  https://www.osfc.io/2018/talks/google-secure-microcontroller-and-ccd-closed-case-debugging/

  The chip provides several functions, including TPM 2.0 like functionality.
  It communicates over SPI or I²C using the FIFO protocol described in the
  TCG PC Client Platform TPM Profile Specification for TPM 2.0 (PTP), sec 6:
  https://trustedcomputinggroup.org/resource/pc-client-platform-tpm-profile-ptp-specification/

properties:
  compatible:
    const: google,cr50

allOf:
  - $ref: tpm-common.yaml#

anyOf:
  - $ref: /schemas/spi/spi-peripheral-props.yaml#
  - $ref: tcg,tpm-tis-i2c.yaml#/properties/reg

required:
  - compatible
  - reg

unevaluatedProperties: false

examples:
  - |
    spi {
        #address-cells = <1>;
        #size-cells = <0>;

        tpm@0 {
            reg = <0>;
            compatible = "google,cr50";
            spi-max-frequency = <800000>;
        };
    };

  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    i2c {
        #address-cells = <1>;
        #size-cells = <0>;

        tpm@50 {
            compatible = "google,cr50";
            reg = <0x50>;
            interrupts-extended = <&pio 88 IRQ_TYPE_EDGE_FALLING>;
            pinctrl-names = "default";
            pinctrl-0 = <&cr50_int>;
        };
    };