1*d5b0e70fSEmmanuel Vadot# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*d5b0e70fSEmmanuel Vadot%YAML 1.2 3*d5b0e70fSEmmanuel Vadot--- 4*d5b0e70fSEmmanuel Vadot$id: http://devicetree.org/schemas/timestamp/nvidia,tegra194-hte.yaml# 5*d5b0e70fSEmmanuel Vadot$schema: http://devicetree.org/meta-schemas/core.yaml# 6*d5b0e70fSEmmanuel Vadot 7*d5b0e70fSEmmanuel Vadottitle: Tegra194 on chip generic hardware timestamping engine (HTE) 8*d5b0e70fSEmmanuel Vadot 9*d5b0e70fSEmmanuel Vadotmaintainers: 10*d5b0e70fSEmmanuel Vadot - Dipen Patel <dipenp@nvidia.com> 11*d5b0e70fSEmmanuel Vadot 12*d5b0e70fSEmmanuel Vadotdescription: 13*d5b0e70fSEmmanuel Vadot Tegra SoC has two instances of generic hardware timestamping engines (GTE) 14*d5b0e70fSEmmanuel Vadot known as GTE GPIO and GTE IRQ, which can monitor subset of GPIO and on chip 15*d5b0e70fSEmmanuel Vadot IRQ lines for the state change respectively, upon detection it will record 16*d5b0e70fSEmmanuel Vadot timestamp (taken from system counter) in its internal hardware FIFO. It has 17*d5b0e70fSEmmanuel Vadot a bitmap array arranged in 32bit slices where each bit represent signal/line 18*d5b0e70fSEmmanuel Vadot to enable or disable for the hardware timestamping. The GTE GPIO monitors 19*d5b0e70fSEmmanuel Vadot GPIO lines from the AON (always on) GPIO controller. 20*d5b0e70fSEmmanuel Vadot 21*d5b0e70fSEmmanuel Vadotproperties: 22*d5b0e70fSEmmanuel Vadot compatible: 23*d5b0e70fSEmmanuel Vadot enum: 24*d5b0e70fSEmmanuel Vadot - nvidia,tegra194-gte-aon 25*d5b0e70fSEmmanuel Vadot - nvidia,tegra194-gte-lic 26*d5b0e70fSEmmanuel Vadot 27*d5b0e70fSEmmanuel Vadot reg: 28*d5b0e70fSEmmanuel Vadot maxItems: 1 29*d5b0e70fSEmmanuel Vadot 30*d5b0e70fSEmmanuel Vadot interrupts: 31*d5b0e70fSEmmanuel Vadot maxItems: 1 32*d5b0e70fSEmmanuel Vadot 33*d5b0e70fSEmmanuel Vadot nvidia,int-threshold: 34*d5b0e70fSEmmanuel Vadot $ref: /schemas/types.yaml#/definitions/uint32 35*d5b0e70fSEmmanuel Vadot description: 36*d5b0e70fSEmmanuel Vadot HTE device generates its interrupt based on this u32 FIFO threshold 37*d5b0e70fSEmmanuel Vadot value. The recommended value is 1. 38*d5b0e70fSEmmanuel Vadot minimum: 1 39*d5b0e70fSEmmanuel Vadot maximum: 256 40*d5b0e70fSEmmanuel Vadot 41*d5b0e70fSEmmanuel Vadot nvidia,slices: 42*d5b0e70fSEmmanuel Vadot $ref: /schemas/types.yaml#/definitions/uint32 43*d5b0e70fSEmmanuel Vadot description: 44*d5b0e70fSEmmanuel Vadot HTE lines are arranged in 32 bit slice where each bit represents different 45*d5b0e70fSEmmanuel Vadot line/signal that it can enable/configure for the timestamp. It is u32 46*d5b0e70fSEmmanuel Vadot property and depends on the HTE instance in the chip. The value 3 is for 47*d5b0e70fSEmmanuel Vadot GPIO GTE and 11 for IRQ GTE. 48*d5b0e70fSEmmanuel Vadot enum: [3, 11] 49*d5b0e70fSEmmanuel Vadot 50*d5b0e70fSEmmanuel Vadot '#timestamp-cells': 51*d5b0e70fSEmmanuel Vadot description: 52*d5b0e70fSEmmanuel Vadot This represents number of line id arguments as specified by the 53*d5b0e70fSEmmanuel Vadot consumers. For the GTE IRQ, this is IRQ number as mentioned in the 54*d5b0e70fSEmmanuel Vadot SoC technical reference manual. For the GTE GPIO, its value is same as 55*d5b0e70fSEmmanuel Vadot mentioned in the nvidia GPIO device tree binding document. 56*d5b0e70fSEmmanuel Vadot const: 1 57*d5b0e70fSEmmanuel Vadot 58*d5b0e70fSEmmanuel Vadotrequired: 59*d5b0e70fSEmmanuel Vadot - compatible 60*d5b0e70fSEmmanuel Vadot - reg 61*d5b0e70fSEmmanuel Vadot - interrupts 62*d5b0e70fSEmmanuel Vadot - nvidia,slices 63*d5b0e70fSEmmanuel Vadot - "#timestamp-cells" 64*d5b0e70fSEmmanuel Vadot 65*d5b0e70fSEmmanuel VadotadditionalProperties: false 66*d5b0e70fSEmmanuel Vadot 67*d5b0e70fSEmmanuel Vadotexamples: 68*d5b0e70fSEmmanuel Vadot - | 69*d5b0e70fSEmmanuel Vadot tegra_hte_aon: timestamp@c1e0000 { 70*d5b0e70fSEmmanuel Vadot compatible = "nvidia,tegra194-gte-aon"; 71*d5b0e70fSEmmanuel Vadot reg = <0xc1e0000 0x10000>; 72*d5b0e70fSEmmanuel Vadot interrupts = <0 13 0x4>; 73*d5b0e70fSEmmanuel Vadot nvidia,int-threshold = <1>; 74*d5b0e70fSEmmanuel Vadot nvidia,slices = <3>; 75*d5b0e70fSEmmanuel Vadot #timestamp-cells = <1>; 76*d5b0e70fSEmmanuel Vadot }; 77*d5b0e70fSEmmanuel Vadot 78*d5b0e70fSEmmanuel Vadot - | 79*d5b0e70fSEmmanuel Vadot tegra_hte_lic: timestamp@3aa0000 { 80*d5b0e70fSEmmanuel Vadot compatible = "nvidia,tegra194-gte-lic"; 81*d5b0e70fSEmmanuel Vadot reg = <0x3aa0000 0x10000>; 82*d5b0e70fSEmmanuel Vadot interrupts = <0 11 0x4>; 83*d5b0e70fSEmmanuel Vadot nvidia,int-threshold = <1>; 84*d5b0e70fSEmmanuel Vadot nvidia,slices = <11>; 85*d5b0e70fSEmmanuel Vadot #timestamp-cells = <1>; 86*d5b0e70fSEmmanuel Vadot }; 87*d5b0e70fSEmmanuel Vadot 88*d5b0e70fSEmmanuel Vadot... 89