1Timer64 2------- 3 4The timer64 node describes C6X event timers. 5 6Required properties: 7 8- compatible: must be "ti,c64x+timer64" 9- reg: base address and size of register region 10- interrupts: interrupt id 11 12Optional properties: 13 14- ti,dscr-dev-enable: Device ID used to enable timer IP through DSCR interface. 15 16- ti,core-mask: on multi-core SoCs, bitmask of cores allowed to use this timer. 17 18Example: 19 timer0: timer@25e0000 { 20 compatible = "ti,c64x+timer64"; 21 ti,core-mask = < 0x01 >; 22 reg = <0x25e0000 0x40>; 23 interrupt-parent = <&megamod_pic>; 24 interrupts = < 16 >; 25 }; 26