1*c66ec88fSEmmanuel VadotTimer64 2*c66ec88fSEmmanuel Vadot------- 3*c66ec88fSEmmanuel Vadot 4*c66ec88fSEmmanuel VadotThe timer64 node describes C6X event timers. 5*c66ec88fSEmmanuel Vadot 6*c66ec88fSEmmanuel VadotRequired properties: 7*c66ec88fSEmmanuel Vadot 8*c66ec88fSEmmanuel Vadot- compatible: must be "ti,c64x+timer64" 9*c66ec88fSEmmanuel Vadot- reg: base address and size of register region 10*c66ec88fSEmmanuel Vadot- interrupts: interrupt id 11*c66ec88fSEmmanuel Vadot 12*c66ec88fSEmmanuel VadotOptional properties: 13*c66ec88fSEmmanuel Vadot 14*c66ec88fSEmmanuel Vadot- ti,dscr-dev-enable: Device ID used to enable timer IP through DSCR interface. 15*c66ec88fSEmmanuel Vadot 16*c66ec88fSEmmanuel Vadot- ti,core-mask: on multi-core SoCs, bitmask of cores allowed to use this timer. 17*c66ec88fSEmmanuel Vadot 18*c66ec88fSEmmanuel VadotExample: 19*c66ec88fSEmmanuel Vadot timer0: timer@25e0000 { 20*c66ec88fSEmmanuel Vadot compatible = "ti,c64x+timer64"; 21*c66ec88fSEmmanuel Vadot ti,core-mask = < 0x01 >; 22*c66ec88fSEmmanuel Vadot reg = <0x25e0000 0x40>; 23*c66ec88fSEmmanuel Vadot interrupt-parent = <&megamod_pic>; 24*c66ec88fSEmmanuel Vadot interrupts = < 16 >; 25*c66ec88fSEmmanuel Vadot }; 26