1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/timer/samsung,exynos4210-mct.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Samsung Exynos SoC Multi Core Timer (MCT) 8 9maintainers: 10 - Krzysztof Kozlowski <krzk@kernel.org> 11 12description: |+ 13 The Samsung's Multi Core Timer (MCT) module includes two main blocks, the 14 global timer and CPU local timers. The global timer is a 64-bit free running 15 up-counter and can generate 4 interrupts when the counter reaches one of the 16 four preset counter values. The CPU local timers are 32-bit free running 17 down-counters and generate an interrupt when the counter expires. There is 18 one CPU local timer instantiated in MCT for every CPU in the system. 19 20properties: 21 compatible: 22 enum: 23 - samsung,exynos4210-mct 24 - samsung,exynos4412-mct 25 26 clocks: 27 minItems: 2 28 maxItems: 2 29 30 clock-names: 31 items: 32 - pattern: "^(fin_pll|mct)$" 33 - pattern: "^(fin_pll|mct)$" 34 35 reg: 36 maxItems: 1 37 38 interrupts: 39 description: | 40 Interrupts should be put in specific order. This is, the local timer 41 interrupts should be specified after the four global timer interrupts 42 have been specified: 43 0: Global Timer Interrupt 0 44 1: Global Timer Interrupt 1 45 2: Global Timer Interrupt 2 46 3: Global Timer Interrupt 3 47 4: Local Timer Interrupt 0 48 5: Local Timer Interrupt 1 49 6: .. 50 7: .. 51 i: Local Timer Interrupt n 52 For MCT block that uses a per-processor interrupt for local timers, such 53 as ones compatible with "samsung,exynos4412-mct", only one local timer 54 interrupt might be specified, meaning that all local timers use the same 55 per processor interrupt. 56 minItems: 5 # 4 Global + 1 local 57 maxItems: 20 # 4 Global + 16 local 58 59required: 60 - compatible 61 - clock-names 62 - clocks 63 - interrupts 64 - reg 65 66additionalProperties: false 67 68examples: 69 - | 70 // In this example, the IP contains two local timers, using separate 71 // interrupts, so two local timer interrupts have been specified, 72 // in addition to four global timer interrupts. 73 #include <dt-bindings/clock/exynos4.h> 74 #include <dt-bindings/interrupt-controller/arm-gic.h> 75 76 timer@10050000 { 77 compatible = "samsung,exynos4210-mct"; 78 reg = <0x10050000 0x800>; 79 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; 80 clock-names = "fin_pll", "mct"; 81 82 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 85 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 86 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 87 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 88 }; 89 90 - | 91 // In this example, the timer interrupts are connected to two separate 92 // interrupt controllers. Hence, an interrupts-extended is needed. 93 #include <dt-bindings/clock/exynos4.h> 94 #include <dt-bindings/interrupt-controller/arm-gic.h> 95 96 timer@101c0000 { 97 compatible = "samsung,exynos4210-mct"; 98 reg = <0x101C0000 0x800>; 99 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; 100 clock-names = "fin_pll", "mct"; 101 102 interrupts-extended = <&gic GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 103 <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 104 <&combiner 12 6>, 105 <&combiner 12 7>, 106 <&gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 107 <&gic GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 108 }; 109 110 - | 111 // In this example, the IP contains four local timers, but using 112 // a per-processor interrupt to handle them. Only one first local 113 // interrupt is specified. 114 #include <dt-bindings/clock/exynos4.h> 115 #include <dt-bindings/interrupt-controller/arm-gic.h> 116 117 timer@10050000 { 118 compatible = "samsung,exynos4412-mct"; 119 reg = <0x10050000 0x800>; 120 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; 121 clock-names = "fin_pll", "mct"; 122 123 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 124 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 125 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 126 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 127 <GIC_PPI 42 IRQ_TYPE_LEVEL_HIGH>; 128 }; 129 130 - | 131 // In this example, the IP contains four local timers, but using 132 // a per-processor interrupt to handle them. All the local timer 133 // interrupts are specified. 134 #include <dt-bindings/clock/exynos4.h> 135 #include <dt-bindings/interrupt-controller/arm-gic.h> 136 137 timer@10050000 { 138 compatible = "samsung,exynos4412-mct"; 139 reg = <0x10050000 0x800>; 140 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; 141 clock-names = "fin_pll", "mct"; 142 143 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 144 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 145 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 146 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 147 <GIC_PPI 42 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_PPI 42 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_PPI 42 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_PPI 42 IRQ_TYPE_LEVEL_HIGH>; 151 }; 152