1NVIDIA Tegra30 timer 2 3The Tegra30 timer provides ten 29-bit timer channels, a single 32-bit free 4running counter, and 5 watchdog modules. The first two channels may also 5trigger a legacy watchdog reset. 6 7Required properties: 8 9- compatible : For Tegra30, must contain "nvidia,tegra30-timer". Otherwise, 10 must contain '"nvidia,<chip>-timer", "nvidia,tegra30-timer"' where 11 <chip> is tegra124 or tegra132. 12- reg : Specifies base physical address and size of the registers. 13- interrupts : A list of 6 interrupts; one per each of timer channels 1 14 through 5, and one for the shared interrupt for the remaining channels. 15- clocks : Must contain one entry, for the module clock. 16 See ../clocks/clock-bindings.txt for details. 17 18timer { 19 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer"; 20 reg = <0x60005000 0x400>; 21 interrupts = <0 0 0x04 22 0 1 0x04 23 0 41 0x04 24 0 42 0x04 25 0 121 0x04 26 0 122 0x04>; 27 clocks = <&tegra_car 214>; 28}; 29