1*c66ec88fSEmmanuel VadotNVIDIA Tegra30 timer 2*c66ec88fSEmmanuel Vadot 3*c66ec88fSEmmanuel VadotThe Tegra30 timer provides ten 29-bit timer channels, a single 32-bit free 4*c66ec88fSEmmanuel Vadotrunning counter, and 5 watchdog modules. The first two channels may also 5*c66ec88fSEmmanuel Vadottrigger a legacy watchdog reset. 6*c66ec88fSEmmanuel Vadot 7*c66ec88fSEmmanuel VadotRequired properties: 8*c66ec88fSEmmanuel Vadot 9*c66ec88fSEmmanuel Vadot- compatible : For Tegra30, must contain "nvidia,tegra30-timer". Otherwise, 10*c66ec88fSEmmanuel Vadot must contain '"nvidia,<chip>-timer", "nvidia,tegra30-timer"' where 11*c66ec88fSEmmanuel Vadot <chip> is tegra124 or tegra132. 12*c66ec88fSEmmanuel Vadot- reg : Specifies base physical address and size of the registers. 13*c66ec88fSEmmanuel Vadot- interrupts : A list of 6 interrupts; one per each of timer channels 1 14*c66ec88fSEmmanuel Vadot through 5, and one for the shared interrupt for the remaining channels. 15*c66ec88fSEmmanuel Vadot- clocks : Must contain one entry, for the module clock. 16*c66ec88fSEmmanuel Vadot See ../clocks/clock-bindings.txt for details. 17*c66ec88fSEmmanuel Vadot 18*c66ec88fSEmmanuel Vadottimer { 19*c66ec88fSEmmanuel Vadot compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer"; 20*c66ec88fSEmmanuel Vadot reg = <0x60005000 0x400>; 21*c66ec88fSEmmanuel Vadot interrupts = <0 0 0x04 22*c66ec88fSEmmanuel Vadot 0 1 0x04 23*c66ec88fSEmmanuel Vadot 0 41 0x04 24*c66ec88fSEmmanuel Vadot 0 42 0x04 25*c66ec88fSEmmanuel Vadot 0 121 0x04 26*c66ec88fSEmmanuel Vadot 0 122 0x04>; 27*c66ec88fSEmmanuel Vadot clocks = <&tegra_car 214>; 28*c66ec88fSEmmanuel Vadot}; 29