1NVIDIA Tegra210 timer 2 3The Tegra210 timer provides fourteen 29-bit timer counters and one 32-bit 4timestamp counter. The TMRs run at either a fixed 1 MHz clock rate derived 5from the oscillator clock (TMR0-TMR9) or directly at the oscillator clock 6(TMR10-TMR13). Each TMR can be programmed to generate one-shot, periodic, 7or watchdog interrupts. 8 9Required properties: 10- compatible : "nvidia,tegra210-timer". 11- reg : Specifies base physical address and size of the registers. 12- interrupts : A list of 14 interrupts; one per each timer channels 0 through 13 13. 14- clocks : Must contain one entry, for the module clock. 15 See ../clocks/clock-bindings.txt for details. 16 17timer@60005000 { 18 compatible = "nvidia,tegra210-timer"; 19 reg = <0x0 0x60005000 0x0 0x400>; 20 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 21 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 22 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 23 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 24 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 25 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 26 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 27 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 28 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 29 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 30 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 31 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 32 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 33 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 34 clocks = <&tegra_car TEGRA210_CLK_TIMER>; 35 clock-names = "timer"; 36}; 37