1*c66ec88fSEmmanuel VadotNVIDIA Tegra20 timer 2*c66ec88fSEmmanuel Vadot 3*c66ec88fSEmmanuel VadotThe Tegra20 timer provides four 29-bit timer channels and a single 32-bit free 4*c66ec88fSEmmanuel Vadotrunning counter. The first two channels may also trigger a watchdog reset. 5*c66ec88fSEmmanuel Vadot 6*c66ec88fSEmmanuel VadotRequired properties: 7*c66ec88fSEmmanuel Vadot 8*c66ec88fSEmmanuel Vadot- compatible : should be "nvidia,tegra20-timer". 9*c66ec88fSEmmanuel Vadot- reg : Specifies base physical address and size of the registers. 10*c66ec88fSEmmanuel Vadot- interrupts : A list of 4 interrupts; one per timer channel. 11*c66ec88fSEmmanuel Vadot- clocks : Must contain one entry, for the module clock. 12*c66ec88fSEmmanuel Vadot See ../clocks/clock-bindings.txt for details. 13*c66ec88fSEmmanuel Vadot 14*c66ec88fSEmmanuel VadotExample: 15*c66ec88fSEmmanuel Vadot 16*c66ec88fSEmmanuel Vadottimer { 17*c66ec88fSEmmanuel Vadot compatible = "nvidia,tegra20-timer"; 18*c66ec88fSEmmanuel Vadot reg = <0x60005000 0x60>; 19*c66ec88fSEmmanuel Vadot interrupts = <0 0 0x04 20*c66ec88fSEmmanuel Vadot 0 1 0x04 21*c66ec88fSEmmanuel Vadot 0 41 0x04 22*c66ec88fSEmmanuel Vadot 0 42 0x04>; 23*c66ec88fSEmmanuel Vadot clocks = <&tegra_car 132>; 24*c66ec88fSEmmanuel Vadot}; 25