1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/timer/arm,sp804.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: ARM sp804 Dual Timers 8 9maintainers: 10 - Haojian Zhuang <haojian.zhuang@linaro.org> 11 12description: |+ 13 The Arm SP804 IP implements two independent timers, configurable for 14 16 or 32 bit operation and capable of running in one-shot, periodic, or 15 free-running mode. The input clock is shared, but can be gated and prescaled 16 independently for each timer. 17 18 There is a viriant of Arm SP804: Hisilicon 64-bit SP804 timer. Some Hisilicon 19 SoCs, such as Hi1212, should use the dedicated compatible: "hisilicon,sp804". 20 21# Need a custom select here or 'arm,primecell' will match on lots of nodes 22select: 23 properties: 24 compatible: 25 contains: 26 enum: 27 - arm,sp804 28 - hisilicon,sp804 29 required: 30 - compatible 31 32properties: 33 compatible: 34 items: 35 - enum: 36 - arm,sp804 37 - hisilicon,sp804 38 - const: arm,primecell 39 40 interrupts: 41 description: | 42 If two interrupts are listed, those are the interrupts for timer 43 1 and 2, respectively. If there is only a single interrupt, it is 44 either a combined interrupt or the sole interrupt of one timer, as 45 specified by the "arm,sp804-has-irq" property. 46 minItems: 1 47 maxItems: 2 48 49 reg: 50 description: The physical base address of the SP804 IP. 51 maxItems: 1 52 53 clocks: 54 description: | 55 Clocks driving the dual timer hardware. This list should 56 be 1 or 3 clocks. With 3 clocks, the order is timer0 clock, timer1 57 clock, apb_pclk. A single clock can also be specified if the same 58 clock is used for all clock inputs. 59 oneOf: 60 - items: 61 - description: clock for timer 1 62 - description: clock for timer 2 63 - description: bus clock 64 - items: 65 - description: unified clock for both timers and the bus 66 67 clock-names: true 68 # The original binding did not specify any clock names, and there is no 69 # consistent naming used in the existing DTs. The primecell binding 70 # requires the "apb_pclk" name, so we need this property. 71 # Use "timer0clk", "timer1clk", "apb_pclk" for new DTs. 72 73 arm,sp804-has-irq: 74 description: If only one interrupt line is connected to the interrupt 75 controller, this property specifies which timer is connected to this 76 line. 77 $ref: /schemas/types.yaml#/definitions/uint32 78 minimum: 1 79 maximum: 2 80 81required: 82 - compatible 83 - interrupts 84 - reg 85 - clocks 86 87additionalProperties: false 88 89examples: 90 - | 91 timer0: timer@fc800000 { 92 compatible = "arm,sp804", "arm,primecell"; 93 reg = <0xfc800000 0x1000>; 94 interrupts = <0 0 4>, <0 1 4>; 95 clocks = <&timclk1>, <&timclk2>, <&pclk>; 96 clock-names = "timer1", "timer2", "apb_pclk"; 97 }; 98