1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/timer/arm,arch_timer.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: ARM architected timer 8 9maintainers: 10 - Marc Zyngier <marc.zyngier@arm.com> 11 - Mark Rutland <mark.rutland@arm.com> 12description: |+ 13 ARM cores may have a per-core architected timer, which provides per-cpu timers, 14 or a memory mapped architected timer, which provides up to 8 frames with a 15 physical and optional virtual timer per frame. 16 17 The per-core architected timer is attached to a GIC to deliver its 18 per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC 19 to deliver its interrupts via SPIs. 20 21properties: 22 compatible: 23 oneOf: 24 - items: 25 - enum: 26 - arm,cortex-a15-timer 27 - enum: 28 - arm,armv7-timer 29 - items: 30 - enum: 31 - arm,armv7-timer 32 - items: 33 - enum: 34 - arm,armv8-timer 35 36 interrupts: 37 minItems: 1 38 maxItems: 5 39 items: 40 - description: secure timer irq 41 - description: non-secure timer irq 42 - description: virtual timer irq 43 - description: hypervisor timer irq 44 - description: hypervisor virtual timer irq 45 46 interrupt-names: 47 oneOf: 48 - minItems: 2 49 items: 50 - const: phys 51 - const: virt 52 - const: hyp-phys 53 - const: hyp-virt 54 - minItems: 3 55 items: 56 - const: sec-phys 57 - const: phys 58 - const: virt 59 - const: hyp-phys 60 - const: hyp-virt 61 62 clock-frequency: 63 description: The frequency of the main counter, in Hz. Should be present 64 only where necessary to work around broken firmware which does not configure 65 CNTFRQ on all CPUs to a uniform correct value. Use of this property is 66 strongly discouraged; fix your firmware unless absolutely impossible. 67 68 always-on: 69 type: boolean 70 description: If present, the timer is powered through an always-on power 71 domain, therefore it never loses context. 72 73 allwinner,erratum-unknown1: 74 type: boolean 75 description: Indicates the presence of an erratum found in Allwinner SoCs, 76 where reading certain values from the counter is unreliable. This also 77 affects writes to the tval register, due to the implicit counter read. 78 79 fsl,erratum-a008585: 80 type: boolean 81 description: Indicates the presence of QorIQ erratum A-008585, which says 82 that reading the counter is unreliable unless the same value is returned 83 by back-to-back reads. This also affects writes to the tval register, due 84 to the implicit counter read. 85 86 hisilicon,erratum-161010101: 87 type: boolean 88 description: Indicates the presence of Hisilicon erratum 161010101, which 89 says that reading the counters is unreliable in some cases, and reads may 90 return a value 32 beyond the correct value. This also affects writes to 91 the tval registers, due to the implicit counter read. 92 93 arm,cpu-registers-not-fw-configured: 94 type: boolean 95 description: Firmware does not initialize any of the generic timer CPU 96 registers, which contain their architecturally-defined reset values. Only 97 supported for 32-bit systems which follow the ARMv7 architected reset 98 values. 99 100 arm,no-tick-in-suspend: 101 type: boolean 102 description: The main counter does not tick when the system is in 103 low-power system suspend on some SoCs. This behavior does not match the 104 Architecture Reference Manual's specification that the system counter "must 105 be implemented in an always-on power domain." 106 107required: 108 - compatible 109 110additionalProperties: false 111 112oneOf: 113 - required: 114 - interrupts 115 - required: 116 - interrupts-extended 117 118examples: 119 - | 120 timer { 121 compatible = "arm,cortex-a15-timer", 122 "arm,armv7-timer"; 123 interrupts = <1 13 0xf08>, 124 <1 14 0xf08>, 125 <1 11 0xf08>, 126 <1 10 0xf08>; 127 clock-frequency = <100000000>; 128 }; 129 130... 131