1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/timer/arm,arch_timer.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: ARM architected timer 8 9maintainers: 10 - Marc Zyngier <marc.zyngier@arm.com> 11 - Mark Rutland <mark.rutland@arm.com> 12description: |+ 13 ARM cores may have a per-core architected timer, which provides per-cpu timers, 14 or a memory mapped architected timer, which provides up to 8 frames with a 15 physical and optional virtual timer per frame. 16 17 The per-core architected timer is attached to a GIC to deliver its 18 per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC 19 to deliver its interrupts via SPIs. 20 21properties: 22 compatible: 23 oneOf: 24 - items: 25 - const: arm,cortex-a15-timer 26 - const: arm,armv7-timer 27 - items: 28 - enum: 29 - arm,armv7-timer 30 - arm,armv8-timer 31 - items: 32 - const: arm,armv8-timer 33 - const: arm,armv7-timer 34 35 interrupts: 36 minItems: 1 37 items: 38 - description: secure timer irq 39 - description: non-secure timer irq 40 - description: virtual timer irq 41 - description: hypervisor timer irq 42 - description: hypervisor virtual timer irq 43 44 interrupt-names: 45 oneOf: 46 - minItems: 2 47 items: 48 - const: phys 49 - const: virt 50 - const: hyp-phys 51 - const: hyp-virt 52 - minItems: 3 53 items: 54 - const: sec-phys 55 - const: phys 56 - const: virt 57 - const: hyp-phys 58 - const: hyp-virt 59 60 clock-frequency: 61 description: The frequency of the main counter, in Hz. Should be present 62 only where necessary to work around broken firmware which does not configure 63 CNTFRQ on all CPUs to a uniform correct value. Use of this property is 64 strongly discouraged; fix your firmware unless absolutely impossible. 65 66 always-on: 67 type: boolean 68 description: If present, the timer is powered through an always-on power 69 domain, therefore it never loses context. 70 71 allwinner,erratum-unknown1: 72 type: boolean 73 description: Indicates the presence of an erratum found in Allwinner SoCs, 74 where reading certain values from the counter is unreliable. This also 75 affects writes to the tval register, due to the implicit counter read. 76 77 fsl,erratum-a008585: 78 type: boolean 79 description: Indicates the presence of QorIQ erratum A-008585, which says 80 that reading the counter is unreliable unless the same value is returned 81 by back-to-back reads. This also affects writes to the tval register, due 82 to the implicit counter read. 83 84 hisilicon,erratum-161010101: 85 type: boolean 86 description: Indicates the presence of Hisilicon erratum 161010101, which 87 says that reading the counters is unreliable in some cases, and reads may 88 return a value 32 beyond the correct value. This also affects writes to 89 the tval registers, due to the implicit counter read. 90 91 arm,cpu-registers-not-fw-configured: 92 type: boolean 93 description: Firmware does not initialize any of the generic timer CPU 94 registers, which contain their architecturally-defined reset values. Only 95 supported for 32-bit systems which follow the ARMv7 architected reset 96 values. 97 98 arm,no-tick-in-suspend: 99 type: boolean 100 description: The main counter does not tick when the system is in 101 low-power system suspend on some SoCs. This behavior does not match the 102 Architecture Reference Manual's specification that the system counter "must 103 be implemented in an always-on power domain." 104 105required: 106 - compatible 107 108additionalProperties: false 109 110oneOf: 111 - required: 112 - interrupts 113 - required: 114 - interrupts-extended 115 116examples: 117 - | 118 timer { 119 compatible = "arm,cortex-a15-timer", 120 "arm,armv7-timer"; 121 interrupts = <1 13 0xf08>, 122 <1 14 0xf08>, 123 <1 11 0xf08>, 124 <1 10 0xf08>; 125 clock-frequency = <100000000>; 126 }; 127 128... 129