1# SPDX-License-Identifier: (GPL-2.0 OR MIT) 2# Copyright 2019 Linaro Ltd. 3%YAML 1.2 4--- 5$id: http://devicetree.org/schemas/thermal/qcom-tsens.yaml# 6$schema: http://devicetree.org/meta-schemas/core.yaml# 7 8title: QCOM SoC Temperature Sensor (TSENS) 9 10maintainers: 11 - Amit Kucheria <amitk@kernel.org> 12 13description: | 14 QCOM SoCs have TSENS IP to allow temperature measurement. There are currently 15 three distinct major versions of the IP that is supported by a single driver. 16 The IP versions are named v0.1, v1 and v2 in the driver, where v0.1 captures 17 everything before v1 when there was no versioning information. 18 19properties: 20 compatible: 21 oneOf: 22 - description: msm8960 TSENS based 23 items: 24 - enum: 25 - qcom,ipq8064-tsens 26 - qcom,msm8960-tsens 27 28 - description: v0.1 of TSENS 29 items: 30 - enum: 31 - qcom,mdm9607-tsens 32 - qcom,msm8226-tsens 33 - qcom,msm8909-tsens 34 - qcom,msm8916-tsens 35 - qcom,msm8939-tsens 36 - qcom,msm8974-tsens 37 - const: qcom,tsens-v0_1 38 39 - description: v1 of TSENS 40 items: 41 - enum: 42 - qcom,msm8956-tsens 43 - qcom,msm8976-tsens 44 - qcom,qcs404-tsens 45 - const: qcom,tsens-v1 46 47 - description: v2 of TSENS 48 items: 49 - enum: 50 - qcom,msm8953-tsens 51 - qcom,msm8996-tsens 52 - qcom,msm8998-tsens 53 - qcom,qcm2290-tsens 54 - qcom,sc7180-tsens 55 - qcom,sc7280-tsens 56 - qcom,sc8180x-tsens 57 - qcom,sc8280xp-tsens 58 - qcom,sdm630-tsens 59 - qcom,sdm845-tsens 60 - qcom,sm6115-tsens 61 - qcom,sm6350-tsens 62 - qcom,sm6375-tsens 63 - qcom,sm8150-tsens 64 - qcom,sm8250-tsens 65 - qcom,sm8350-tsens 66 - qcom,sm8450-tsens 67 - qcom,sm8550-tsens 68 - const: qcom,tsens-v2 69 70 - description: v2 of TSENS with combined interrupt 71 enum: 72 - qcom,ipq8074-tsens 73 74 - description: v2 of TSENS with combined interrupt 75 items: 76 - enum: 77 - qcom,ipq9574-tsens 78 - const: qcom,ipq8074-tsens 79 80 reg: 81 items: 82 - description: TM registers 83 - description: SROT registers 84 85 interrupts: 86 minItems: 1 87 maxItems: 2 88 89 interrupt-names: 90 minItems: 1 91 maxItems: 2 92 93 nvmem-cells: 94 oneOf: 95 - minItems: 1 96 maxItems: 2 97 description: 98 Reference to an nvmem node for the calibration data 99 - minItems: 5 100 maxItems: 35 101 description: | 102 Reference to nvmem cells for the calibration mode, two calibration 103 bases and two cells per each sensor 104 # special case for msm8974 / apq8084 105 - maxItems: 51 106 description: | 107 Reference to nvmem cells for the calibration mode, two calibration 108 bases and two cells per each sensor, main and backup copies, plus use_backup cell 109 110 nvmem-cell-names: 111 oneOf: 112 - minItems: 1 113 items: 114 - const: calib 115 - enum: 116 - calib_backup 117 - calib_sel 118 - minItems: 5 119 items: 120 - const: mode 121 - const: base1 122 - const: base2 123 - pattern: '^s[0-9]+_p1$' 124 - pattern: '^s[0-9]+_p2$' 125 - pattern: '^s[0-9]+_p1$' 126 - pattern: '^s[0-9]+_p2$' 127 - pattern: '^s[0-9]+_p1$' 128 - pattern: '^s[0-9]+_p2$' 129 - pattern: '^s[0-9]+_p1$' 130 - pattern: '^s[0-9]+_p2$' 131 - pattern: '^s[0-9]+_p1$' 132 - pattern: '^s[0-9]+_p2$' 133 - pattern: '^s[0-9]+_p1$' 134 - pattern: '^s[0-9]+_p2$' 135 - pattern: '^s[0-9]+_p1$' 136 - pattern: '^s[0-9]+_p2$' 137 - pattern: '^s[0-9]+_p1$' 138 - pattern: '^s[0-9]+_p2$' 139 - pattern: '^s[0-9]+_p1$' 140 - pattern: '^s[0-9]+_p2$' 141 - pattern: '^s[0-9]+_p1$' 142 - pattern: '^s[0-9]+_p2$' 143 - pattern: '^s[0-9]+_p1$' 144 - pattern: '^s[0-9]+_p2$' 145 - pattern: '^s[0-9]+_p1$' 146 - pattern: '^s[0-9]+_p2$' 147 - pattern: '^s[0-9]+_p1$' 148 - pattern: '^s[0-9]+_p2$' 149 - pattern: '^s[0-9]+_p1$' 150 - pattern: '^s[0-9]+_p2$' 151 - pattern: '^s[0-9]+_p1$' 152 - pattern: '^s[0-9]+_p2$' 153 - pattern: '^s[0-9]+_p1$' 154 - pattern: '^s[0-9]+_p2$' 155 # special case for msm8974 / apq8084 156 - items: 157 - const: mode 158 - const: base1 159 - const: base2 160 - const: use_backup 161 - const: mode_backup 162 - const: base1_backup 163 - const: base2_backup 164 - const: s0_p1 165 - const: s0_p2 166 - const: s1_p1 167 - const: s1_p2 168 - const: s2_p1 169 - const: s2_p2 170 - const: s3_p1 171 - const: s3_p2 172 - const: s4_p1 173 - const: s4_p2 174 - const: s5_p1 175 - const: s5_p2 176 - const: s6_p1 177 - const: s6_p2 178 - const: s7_p1 179 - const: s7_p2 180 - const: s8_p1 181 - const: s8_p2 182 - const: s9_p1 183 - const: s9_p2 184 - const: s10_p1 185 - const: s10_p2 186 - const: s0_p1_backup 187 - const: s0_p2_backup 188 - const: s1_p1_backup 189 - const: s1_p2_backup 190 - const: s2_p1_backup 191 - const: s2_p2_backup 192 - const: s3_p1_backup 193 - const: s3_p2_backup 194 - const: s4_p1_backup 195 - const: s4_p2_backup 196 - const: s5_p1_backup 197 - const: s5_p2_backup 198 - const: s6_p1_backup 199 - const: s6_p2_backup 200 - const: s7_p1_backup 201 - const: s7_p2_backup 202 - const: s8_p1_backup 203 - const: s8_p2_backup 204 - const: s9_p1_backup 205 - const: s9_p2_backup 206 - const: s10_p1_backup 207 - const: s10_p2_backup 208 209 "#qcom,sensors": 210 description: 211 Number of sensors enabled on this platform 212 $ref: /schemas/types.yaml#/definitions/uint32 213 minimum: 1 214 maximum: 16 215 216 "#thermal-sensor-cells": 217 const: 1 218 description: 219 Number of cells required to uniquely identify the thermal sensors. Since 220 we have multiple sensors this is set to 1 221 222required: 223 - compatible 224 - interrupts 225 - interrupt-names 226 - "#thermal-sensor-cells" 227 - "#qcom,sensors" 228 229allOf: 230 - if: 231 properties: 232 compatible: 233 contains: 234 enum: 235 - qcom,ipq8064-tsens 236 - qcom,msm8960-tsens 237 - qcom,tsens-v0_1 238 - qcom,tsens-v1 239 then: 240 properties: 241 interrupts: 242 items: 243 - description: Combined interrupt if upper or lower threshold crossed 244 interrupt-names: 245 items: 246 - const: uplow 247 248 - if: 249 properties: 250 compatible: 251 contains: 252 const: qcom,tsens-v2 253 then: 254 properties: 255 interrupts: 256 items: 257 - description: Combined interrupt if upper or lower threshold crossed 258 - description: Interrupt if critical threshold crossed 259 interrupt-names: 260 items: 261 - const: uplow 262 - const: critical 263 264 - if: 265 properties: 266 compatible: 267 contains: 268 enum: 269 - qcom,ipq8074-tsens 270 then: 271 properties: 272 interrupts: 273 items: 274 - description: Combined interrupt if upper, lower or critical thresholds crossed 275 interrupt-names: 276 items: 277 - const: combined 278 279 - if: 280 properties: 281 compatible: 282 contains: 283 enum: 284 - qcom,ipq8074-tsens 285 - qcom,tsens-v0_1 286 - qcom,tsens-v1 287 - qcom,tsens-v2 288 289 then: 290 required: 291 - reg 292 293additionalProperties: false 294 295examples: 296 - | 297 #include <dt-bindings/interrupt-controller/arm-gic.h> 298 // Example msm9860 based SoC (ipq8064): 299 gcc: clock-controller { 300 301 /* ... */ 302 303 tsens: thermal-sensor { 304 compatible = "qcom,ipq8064-tsens"; 305 306 nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>; 307 nvmem-cell-names = "calib", "calib_backup"; 308 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 309 interrupt-names = "uplow"; 310 311 #qcom,sensors = <11>; 312 #thermal-sensor-cells = <1>; 313 }; 314 }; 315 316 - | 317 #include <dt-bindings/interrupt-controller/arm-gic.h> 318 // Example 1 (new calbiration data: for pre v1 IP): 319 thermal-sensor@4a9000 { 320 compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1"; 321 reg = <0x4a9000 0x1000>, /* TM */ 322 <0x4a8000 0x1000>; /* SROT */ 323 324 nvmem-cells = <&tsens_mode>, 325 <&tsens_base1>, <&tsens_base2>, 326 <&tsens_s0_p1>, <&tsens_s0_p2>, 327 <&tsens_s1_p1>, <&tsens_s1_p2>, 328 <&tsens_s2_p1>, <&tsens_s2_p2>, 329 <&tsens_s4_p1>, <&tsens_s4_p2>, 330 <&tsens_s5_p1>, <&tsens_s5_p2>; 331 nvmem-cell-names = "mode", 332 "base1", "base2", 333 "s0_p1", "s0_p2", 334 "s1_p1", "s1_p2", 335 "s2_p1", "s2_p2", 336 "s4_p1", "s4_p2", 337 "s5_p1", "s5_p2"; 338 339 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 340 interrupt-names = "uplow"; 341 342 #qcom,sensors = <5>; 343 #thermal-sensor-cells = <1>; 344 }; 345 346 - | 347 #include <dt-bindings/interrupt-controller/arm-gic.h> 348 // Example 1 (legacy: for pre v1 IP): 349 tsens1: thermal-sensor@4a9000 { 350 compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1"; 351 reg = <0x4a9000 0x1000>, /* TM */ 352 <0x4a8000 0x1000>; /* SROT */ 353 354 nvmem-cells = <&tsens_caldata>, <&tsens_calsel>; 355 nvmem-cell-names = "calib", "calib_sel"; 356 357 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 358 interrupt-names = "uplow"; 359 360 #qcom,sensors = <5>; 361 #thermal-sensor-cells = <1>; 362 }; 363 364 - | 365 #include <dt-bindings/interrupt-controller/arm-gic.h> 366 // Example 2 (for any platform containing v1 of the TSENS IP): 367 tsens2: thermal-sensor@4a9000 { 368 compatible = "qcom,qcs404-tsens", "qcom,tsens-v1"; 369 reg = <0x004a9000 0x1000>, /* TM */ 370 <0x004a8000 0x1000>; /* SROT */ 371 372 nvmem-cells = <&tsens_caldata>; 373 nvmem-cell-names = "calib"; 374 375 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>; 376 interrupt-names = "uplow"; 377 378 #qcom,sensors = <10>; 379 #thermal-sensor-cells = <1>; 380 }; 381 382 - | 383 #include <dt-bindings/interrupt-controller/arm-gic.h> 384 // Example 3 (for any platform containing v2 of the TSENS IP): 385 tsens3: thermal-sensor@c263000 { 386 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; 387 reg = <0xc263000 0x1ff>, 388 <0xc222000 0x1ff>; 389 390 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 391 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 392 interrupt-names = "uplow", "critical"; 393 394 #qcom,sensors = <13>; 395 #thermal-sensor-cells = <1>; 396 }; 397 398 - | 399 #include <dt-bindings/interrupt-controller/arm-gic.h> 400 // Example 4 (for any IPQ8074 based SoC-s): 401 tsens4: thermal-sensor@4a9000 { 402 compatible = "qcom,ipq8074-tsens"; 403 reg = <0x4a9000 0x1000>, 404 <0x4a8000 0x1000>; 405 406 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 407 interrupt-names = "combined"; 408 409 #qcom,sensors = <16>; 410 #thermal-sensor-cells = <1>; 411 }; 412... 413