xref: /freebsd/sys/contrib/device-tree/Bindings/sram/sram.yaml (revision 7fdf597e96a02165cfe22ff357b857d5fa15ed8a)
1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/sram/sram.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Generic on-chip SRAM
8
9maintainers:
10  - Rob Herring <robh@kernel.org>
11
12description: |+
13  Simple IO memory regions to be managed by the genalloc API.
14
15  Each child of the sram node specifies a region of reserved memory. Each
16  child node should use a 'reg' property to specify a specific range of
17  reserved memory.
18
19  Following the generic-names recommended practice, node names should
20  reflect the purpose of the node. Unit address (@<address>) should be
21  appended to the name.
22
23properties:
24  $nodename:
25    pattern: "^sram(@.*)?"
26
27  compatible:
28    contains:
29      enum:
30        - mmio-sram
31        - amlogic,meson-gxbb-sram
32        - arm,juno-sram-ns
33        - atmel,sama5d2-securam
34        - nvidia,tegra186-sysram
35        - nvidia,tegra194-sysram
36        - nvidia,tegra234-sysram
37        - qcom,rpm-msg-ram
38        - rockchip,rk3288-pmu-sram
39
40  reg:
41    maxItems: 1
42
43  clocks:
44    maxItems: 1
45    description:
46      A list of phandle and clock specifier pair that controls the single
47      SRAM clock.
48
49  "#address-cells":
50    const: 1
51
52  "#size-cells":
53    const: 1
54
55  ranges:
56    maxItems: 1
57    description:
58      Should translate from local addresses within the sram to bus addresses.
59
60  no-memory-wc:
61    description:
62      The flag indicating, that SRAM memory region has not to be remapped
63      as write combining. WC is used by default.
64    type: boolean
65
66patternProperties:
67  "^([a-z0-9]*-)?sram(-section)?@[a-f0-9]+$":
68    type: object
69    description:
70      Each child of the sram node specifies a region of reserved memory.
71    properties:
72      compatible:
73        description:
74          Should contain a vendor specific string in the form
75          <vendor>,[<device>-]<usage>
76        contains:
77          enum:
78            - allwinner,sun4i-a10-sram-a3-a4
79            - allwinner,sun4i-a10-sram-c1
80            - allwinner,sun4i-a10-sram-d
81            - allwinner,sun9i-a80-smp-sram
82            - allwinner,sun50i-a64-sram-c
83            - amlogic,meson8-ao-arc-sram
84            - amlogic,meson8b-ao-arc-sram
85            - amlogic,meson8-smp-sram
86            - amlogic,meson8b-smp-sram
87            - amlogic,meson-gxbb-scp-shmem
88            - amlogic,meson-axg-scp-shmem
89            - arm,juno-scp-shmem
90            - arm,scmi-shmem
91            - arm,scp-shmem
92            - renesas,smp-sram
93            - rockchip,rk3066-smp-sram
94            - samsung,exynos4210-sysram
95            - samsung,exynos4210-sysram-ns
96            - socionext,milbeaut-smp-sram
97            - stericsson,u8500-esram
98
99      reg:
100        description:
101          IO mem address range, relative to the SRAM range.
102        maxItems: 1
103
104      pool:
105        description:
106          Indicates that the particular reserved SRAM area is addressable
107          and in use by another device or devices.
108        type: boolean
109
110      export:
111        description:
112          Indicates that the reserved SRAM area may be accessed outside
113          of the kernel, e.g. by bootloader or userspace.
114        type: boolean
115
116      protect-exec:
117        description: |
118          Same as 'pool' above but with the additional constraint that code
119          will be run from the region and that the memory is maintained as
120          read-only, executable during code execution. NOTE: This region must
121          be page aligned on start and end in order to properly allow
122          manipulation of the page attributes.
123        type: boolean
124
125      label:
126        description:
127          The name for the reserved partition, if omitted, the label is taken
128          from the node name excluding the unit address.
129
130    required:
131      - reg
132
133    additionalProperties: false
134
135required:
136  - compatible
137  - reg
138
139if:
140  not:
141    properties:
142      compatible:
143        contains:
144          enum:
145            - qcom,rpm-msg-ram
146            - rockchip,rk3288-pmu-sram
147then:
148  required:
149    - "#address-cells"
150    - "#size-cells"
151    - ranges
152
153additionalProperties: false
154
155examples:
156  - |
157    sram@5c000000 {
158        compatible = "mmio-sram";
159        reg = <0x5c000000 0x40000>; /* 256 KiB SRAM at address 0x5c000000 */
160
161        #address-cells = <1>;
162        #size-cells = <1>;
163        ranges = <0 0x5c000000 0x40000>;
164
165        smp-sram@100 {
166            reg = <0x100 0x50>;
167        };
168
169        device-sram@1000 {
170            reg = <0x1000 0x1000>;
171            pool;
172        };
173
174        exported-sram@20000 {
175            reg = <0x20000 0x20000>;
176            export;
177        };
178    };
179
180  - |
181    // Samsung SMP-capable Exynos SoCs use part of the SYSRAM for the bringup
182    // of the secondary cores. Once the core gets powered up it executes the
183    // code that is residing at some specific location of the SYSRAM.
184    //
185    // Therefore reserved section sub-nodes have to be added to the mmio-sram
186    // declaration. These nodes are of two types depending upon secure or
187    // non-secure execution environment.
188    sram@2020000 {
189        compatible = "mmio-sram";
190        reg = <0x02020000 0x54000>;
191        #address-cells = <1>;
192        #size-cells = <1>;
193        ranges = <0 0x02020000 0x54000>;
194
195        smp-sram@0 {
196            compatible = "samsung,exynos4210-sysram";
197            reg = <0x0 0x1000>;
198        };
199
200        smp-sram@53000 {
201            compatible = "samsung,exynos4210-sysram-ns";
202            reg = <0x53000 0x1000>;
203        };
204    };
205
206  - |
207    // Amlogic's SMP-capable SoCs use part of the sram for the bringup of the cores.
208    // Once the core gets powered up it executes the code that is residing at a
209    // specific location.
210    //
211    // Therefore a reserved section sub-node has to be added to the mmio-sram
212    // declaration.
213    sram@d9000000 {
214        compatible = "mmio-sram";
215        reg = <0xd9000000 0x20000>;
216        #address-cells = <1>;
217        #size-cells = <1>;
218        ranges = <0 0xd9000000 0x20000>;
219
220        smp-sram@1ff80 {
221            compatible = "amlogic,meson8b-smp-sram";
222            reg = <0x1ff80 0x8>;
223        };
224    };
225
226  - |
227    sram@e63c0000 {
228        compatible = "mmio-sram";
229        reg = <0xe63c0000 0x1000>;
230        #address-cells = <1>;
231        #size-cells = <1>;
232        ranges = <0 0xe63c0000 0x1000>;
233
234        smp-sram@0 {
235            compatible = "renesas,smp-sram";
236            reg = <0 0x10>;
237        };
238    };
239
240  - |
241    sram@10080000 {
242        compatible = "mmio-sram";
243        reg = <0x10080000 0x10000>;
244        #address-cells = <1>;
245        #size-cells = <1>;
246        ranges;
247
248        smp-sram@10080000 {
249            compatible = "rockchip,rk3066-smp-sram";
250            reg = <0x10080000 0x50>;
251        };
252    };
253
254  - |
255    // Rockchip's rk3288 SoC uses the sram of pmu to store the function of
256    // resume from maskrom(the 1st level loader). This is a common use of
257    // the "pmu-sram" because it keeps power even in low power states
258    // in the system.
259    sram@ff720000 {
260      compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
261      reg = <0xff720000 0x1000>;
262    };
263
264  - |
265    // Allwinner's A80 SoC uses part of the secure sram for hotplugging of the
266    // primary core (cpu0). Once the core gets powered up it checks if a magic
267    // value is set at a specific location. If it is then the BROM will jump
268    // to the software entry address, instead of executing a standard boot.
269    //
270    // Also there are no "secure-only" properties. The implementation should
271    // check if this SRAM is usable first.
272    sram@20000 {
273        // 256 KiB secure SRAM at 0x20000
274        compatible = "mmio-sram";
275        reg = <0x00020000 0x40000>;
276        #address-cells = <1>;
277        #size-cells = <1>;
278        ranges = <0 0x00020000 0x40000>;
279
280        smp-sram@1000 {
281            // This is checked by BROM to determine if
282            // cpu0 should jump to SMP entry vector
283            compatible = "allwinner,sun9i-a80-smp-sram";
284            reg = <0x1000 0x8>;
285        };
286    };
287
288  - |
289    sram@0 {
290        compatible = "mmio-sram";
291        reg = <0x0 0x10000>;
292        #address-cells = <1>;
293        #size-cells = <1>;
294        ranges = <0 0x0 0x10000>;
295
296        smp-sram@f100 {
297            compatible = "socionext,milbeaut-smp-sram";
298            reg = <0xf100 0x20>;
299        };
300    };
301