xref: /freebsd/sys/contrib/device-tree/Bindings/spi/st,stm32-qspi.yaml (revision c66ec88fed842fbaad62c30d510644ceb7bd2d71) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/spi/st,stm32-qspi.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: STMicroelectronics STM32 Quad Serial Peripheral Interface (QSPI) bindings
8
9maintainers:
10  - Christophe Kerello <christophe.kerello@st.com>
11  - Patrice Chotard <patrice.chotard@st.com>
12
13allOf:
14  - $ref: "spi-controller.yaml#"
15
16properties:
17  compatible:
18    const: st,stm32f469-qspi
19
20  reg:
21    items:
22      - description: registers
23      - description: memory mapping
24
25  reg-names:
26    items:
27      - const: qspi
28      - const: qspi_mm
29
30  clocks:
31    maxItems: 1
32
33  interrupts:
34    maxItems: 1
35
36  resets:
37    maxItems: 1
38
39  dmas:
40    items:
41      - description: tx DMA channel
42      - description: rx DMA channel
43
44  dma-names:
45    items:
46      - const: tx
47      - const: rx
48
49required:
50  - compatible
51  - reg
52  - reg-names
53  - clocks
54  - interrupts
55
56examples:
57  - |
58    #include <dt-bindings/interrupt-controller/arm-gic.h>
59    #include <dt-bindings/clock/stm32mp1-clks.h>
60    #include <dt-bindings/reset/stm32mp1-resets.h>
61    spi@58003000 {
62      compatible = "st,stm32f469-qspi";
63      reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
64      reg-names = "qspi", "qspi_mm";
65      interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
66      dmas = <&mdma1 22 0x10 0x100002 0x0 0x0>,
67             <&mdma1 22 0x10 0x100008 0x0 0x0>;
68      dma-names = "tx", "rx";
69      clocks = <&rcc QSPI_K>;
70      resets = <&rcc QSPI_R>;
71
72      #address-cells = <1>;
73      #size-cells = <0>;
74
75      flash@0 {
76        compatible = "jedec,spi-nor";
77        reg = <0>;
78        spi-rx-bus-width = <4>;
79        spi-max-frequency = <108000000>;
80      };
81    };
82
83...
84