1Spreadtrum ADI controller 2 3ADI is the abbreviation of Anolog-Digital interface, which is used to access 4analog chip (such as PMIC) from digital chip. ADI controller follows the SPI 5framework for its hardware implementation is alike to SPI bus and its timing 6is compatile to SPI timing. 7 8ADI controller has 50 channels including 2 software read/write channels and 948 hardware channels to access analog chip. For 2 software read/write channels, 10users should set ADI registers to access analog chip. For hardware channels, 11we can configure them to allow other hardware components to use it independently, 12which means we can just link one analog chip address to one hardware channel, 13then users can access the mapped analog chip address by this hardware channel 14triggered by hardware components instead of ADI software channels. 15 16Thus we introduce one property named "sprd,hw-channels" to configure hardware 17channels, the first value specifies the hardware channel id which is used to 18transfer data triggered by hardware automatically, and the second value specifies 19the analog chip address where user want to access by hardware components. 20 21Since we have multi-subsystems will use unique ADI to access analog chip, when 22one system is reading/writing data by ADI software channels, that should be under 23one hardware spinlock protection to prevent other systems from reading/writing 24data by ADI software channels at the same time, or two parallel routine of setting 25ADI registers will make ADI controller registers chaos to lead incorrect results. 26Then we need one hardware spinlock to synchronize between the multiple subsystems. 27 28The new version ADI controller supplies multiple master channels for different 29subsystem accessing, that means no need to add hardware spinlock to synchronize, 30thus change the hardware spinlock support to be optional to keep backward 31compatibility. 32 33Required properties: 34- compatible: Should be "sprd,sc9860-adi". 35- reg: Offset and length of ADI-SPI controller register space. 36- #address-cells: Number of cells required to define a chip select address 37 on the ADI-SPI bus. Should be set to 1. 38- #size-cells: Size of cells required to define a chip select address size 39 on the ADI-SPI bus. Should be set to 0. 40 41Optional properties: 42- hwlocks: Reference to a phandle of a hwlock provider node. 43- hwlock-names: Reference to hwlock name strings defined in the same order 44 as the hwlocks, should be "adi". 45- sprd,hw-channels: This is an array of channel values up to 49 channels. 46 The first value specifies the hardware channel id which is used to 47 transfer data triggered by hardware automatically, and the second 48 value specifies the analog chip address where user want to access 49 by hardware components. 50 51SPI slave nodes must be children of the SPI controller node and can contain 52properties described in Documentation/devicetree/bindings/spi/spi-bus.txt. 53 54Example: 55 adi_bus: spi@40030000 { 56 compatible = "sprd,sc9860-adi"; 57 reg = <0 0x40030000 0 0x10000>; 58 hwlocks = <&hwlock1 0>; 59 hwlock-names = "adi"; 60 #address-cells = <1>; 61 #size-cells = <0>; 62 sprd,hw-channels = <30 0x8c20>; 63 }; 64