1Binding for MTK SPI Slave controller 2 3Required properties: 4- compatible: should be one of the following. 5 - mediatek,mt2712-spi-slave: for mt2712 platforms 6- reg: Address and length of the register set for the device. 7- interrupts: Should contain spi interrupt. 8- clocks: phandles to input clocks. 9 It's clock gate, and should be <&infracfg CLK_INFRA_AO_SPI1>. 10- clock-names: should be "spi" for the clock gate. 11 12Optional properties: 13- assigned-clocks: it's mux clock, should be <&topckgen CLK_TOP_SPISLV_SEL>. 14- assigned-clock-parents: parent of mux clock. 15 It's PLL, and should be one of the following. 16 - <&topckgen CLK_TOP_UNIVPLL1_D2>: specify parent clock 312MHZ. 17 It's the default one. 18 - <&topckgen CLK_TOP_UNIVPLL1_D4>: specify parent clock 156MHZ. 19 - <&topckgen CLK_TOP_UNIVPLL2_D4>: specify parent clock 104MHZ. 20 - <&topckgen CLK_TOP_UNIVPLL1_D8>: specify parent clock 78MHZ. 21 22Example: 23- SoC Specific Portion: 24spis1: spi@10013000 { 25 compatible = "mediatek,mt2712-spi-slave"; 26 reg = <0 0x10013000 0 0x100>; 27 interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_LOW>; 28 clocks = <&infracfg CLK_INFRA_AO_SPI1>; 29 clock-names = "spi"; 30 assigned-clocks = <&topckgen CLK_TOP_SPISLV_SEL>; 31 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>; 32}; 33