1Davinci SPI controller device bindings 2 3Links on DM: 4Keystone 2 - https://www.ti.com/lit/ug/sprugp2a/sprugp2a.pdf 5dm644x - https://www.ti.com/lit/ug/sprue32a/sprue32a.pdf 6OMAP-L138/da830 - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf 7 8Required properties: 9- #address-cells: number of cells required to define a chip select 10 address on the SPI bus. Should be set to 1. 11- #size-cells: should be zero. 12- compatible: 13 - "ti,dm6441-spi" for SPI used similar to that on DM644x SoC family 14 - "ti,da830-spi" for SPI used similar to that on DA8xx SoC family 15 - "ti,keystone-spi" for SPI used similar to that on Keystone2 SoC 16 family 17- reg: Offset and length of SPI controller register space 18- num-cs: Number of chip selects. This includes internal as well as 19 GPIO chip selects. 20- ti,davinci-spi-intr-line: interrupt line used to connect the SPI 21 IP to the interrupt controller within the SoC. Possible values 22 are 0 and 1. Manual says one of the two possible interrupt 23 lines can be tied to the interrupt controller. Set this 24 based on a specific SoC configuration. 25- interrupts: interrupt number mapped to CPU. 26- clocks: spi clk phandle 27 For 66AK2G this property should be set per binding, 28 Documentation/devicetree/bindings/clock/ti,sci-clk.yaml 29 30SoC-specific Required Properties: 31 32The following are mandatory properties for Keystone 2 66AK2G SoCs only: 33 34- power-domains: Should contain a phandle to a PM domain provider node 35 and an args specifier containing the SPI device id 36 value. This property is as per the binding, 37 38Optional: 39- cs-gpios: gpio chip selects 40 For example to have 3 internal CS and 2 GPIO CS, user could define 41 cs-gpios = <0>, <0>, <0>, <&gpio1 30 0>, <&gpio1 31 0>; 42 where first three are internal CS and last two are GPIO CS. 43 44Optional properties for slave devices: 45SPI slave nodes can contain the following properties. 46Not all SPI Peripherals from Texas Instruments support this. 47Please check SPI peripheral documentation for a device before using these. 48 49- ti,spi-wdelay : delay between transmission of words 50 (SPIFMTn.WDELAY, SPIDAT1.WDEL) must be specified in number of SPI module 51 clock periods. 52 53 delay = WDELAY * SPI_module_clock_period + 2 * SPI_module_clock_period 54 55Below is timing diagram which shows functional meaning of 56"ti,spi-wdelay" parameter. 57 58 +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ 59SPI_CLK | | | | | | | | | | | | | | | | 60 +----------+ +-+ +-+ +-+ +-+ +---------------------------+ +-+ +-+ +- 61 62SPI_SOMI/SIMO+-----------------+ +----------- 63 +----------+ word1 +---------------------------+word2 64 +-----------------+ +----------- 65 WDELAY 66 <--------------------------> 67 68Example of a NOR flash slave device (n25q032) connected to DaVinci 69SPI controller device over the SPI bus. 70 71spi0:spi@20bf0000 { 72 #address-cells = <1>; 73 #size-cells = <0>; 74 compatible = "ti,dm6446-spi"; 75 reg = <0x20BF0000 0x1000>; 76 num-cs = <4>; 77 ti,davinci-spi-intr-line = <0>; 78 interrupts = <338>; 79 clocks = <&clkspi>; 80 81 flash: n25q032@0 { 82 #address-cells = <1>; 83 #size-cells = <1>; 84 compatible = "st,m25p32"; 85 spi-max-frequency = <25000000>; 86 reg = <0>; 87 ti,spi-wdelay = <8>; 88 89 partition@0 { 90 label = "u-boot-spl"; 91 reg = <0x0 0x80000>; 92 read-only; 93 }; 94 95 partition@1 { 96 label = "test"; 97 reg = <0x80000 0x380000>; 98 }; 99 }; 100}; 101