xref: /freebsd/sys/contrib/device-tree/Bindings/spi/snps,dw-apb-ssi.yaml (revision 2e3507c25e42292b45a5482e116d278f5515d04d) 
1# SPDX-License-Identifier: GPL-2.0-only
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/spi/snps,dw-apb-ssi.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface
8
9maintainers:
10  - Mark Brown <broonie@kernel.org>
11
12allOf:
13  - $ref: spi-controller.yaml#
14  - if:
15      properties:
16        compatible:
17          contains:
18            enum:
19              - mscc,ocelot-spi
20              - mscc,jaguar2-spi
21    then:
22      properties:
23        reg:
24          minItems: 2
25  - if:
26      properties:
27        compatible:
28          contains:
29            enum:
30              - baikal,bt1-sys-ssi
31    then:
32      properties:
33        mux-controls:
34          maxItems: 1
35      required:
36        - mux-controls
37    else:
38      required:
39        - interrupts
40  - if:
41      properties:
42        compatible:
43          contains:
44            const: amd,pensando-elba-spi
45    then:
46      required:
47        - amd,pensando-elba-syscon
48    else:
49      properties:
50        amd,pensando-elba-syscon: false
51
52properties:
53  compatible:
54    oneOf:
55      - description: Generic DW SPI Controller
56        enum:
57          - snps,dw-apb-ssi
58          - snps,dwc-ssi-1.01a
59      - description: Microsemi Ocelot/Jaguar2 SoC SPI Controller
60        items:
61          - enum:
62              - mscc,ocelot-spi
63              - mscc,jaguar2-spi
64          - const: snps,dw-apb-ssi
65      - description: Microchip Sparx5 SoC SPI Controller
66        const: microchip,sparx5-spi
67      - description: Amazon Alpine SPI Controller
68        const: amazon,alpine-dw-apb-ssi
69      - description: Renesas RZ/N1 SPI Controller
70        items:
71          - const: renesas,rzn1-spi
72          - const: snps,dw-apb-ssi
73      - description: Intel Keem Bay SPI Controller
74        const: intel,keembay-ssi
75      - description: Intel Thunder Bay SPI Controller
76        const: intel,thunderbay-ssi
77      - description: AMD Pensando Elba SoC SPI Controller
78        const: amd,pensando-elba-spi
79      - description: Baikal-T1 SPI Controller
80        const: baikal,bt1-ssi
81      - description: Baikal-T1 System Boot SPI Controller
82        const: baikal,bt1-sys-ssi
83      - description: Canaan Kendryte K210 SoS SPI Controller
84        const: canaan,k210-spi
85      - description: Renesas RZ/N1 SPI Controller
86        items:
87          - enum:
88              - renesas,r9a06g032-spi # RZ/N1D
89              - renesas,r9a06g033-spi # RZ/N1S
90          - const: renesas,rzn1-spi   # RZ/N1
91
92  reg:
93    minItems: 1
94    items:
95      - description: DW APB SSI controller memory mapped registers
96      - description: SPI MST region map or directly mapped SPI ROM
97
98  interrupts:
99    maxItems: 1
100
101  clocks:
102    minItems: 1
103    items:
104      - description: SPI Controller reference clock source
105      - description: APB interface clock source
106
107  clock-names:
108    minItems: 1
109    items:
110      - const: ssi_clk
111      - const: pclk
112
113  resets:
114    maxItems: 1
115
116  reset-names:
117    const: spi
118
119  reg-io-width:
120    description: I/O register width (in bytes) implemented by this device
121    default: 4
122    enum: [ 2, 4 ]
123
124  num-cs:
125    default: 4
126    minimum: 1
127    maximum: 4
128
129  dmas:
130    items:
131      - description: TX DMA Channel
132      - description: RX DMA Channel
133
134  dma-names:
135    items:
136      - const: tx
137      - const: rx
138
139  rx-sample-delay-ns:
140    default: 0
141    description: |
142      Default value of the rx-sample-delay-ns property.
143      This value will be used if the property is not explicitly defined
144      for a SPI slave device.
145
146      SPI Rx sample delay offset, unit is nanoseconds.
147      The delay from the default sample time before the actual sample of the
148      rxd input signal occurs. The "rx_sample_delay" is an optional feature
149      of the designware controller, and the upper limit is also subject to
150      controller configuration.
151
152  amd,pensando-elba-syscon:
153    $ref: /schemas/types.yaml#/definitions/phandle-array
154    description:
155      Block address to control SPI chip-selects. The Elba SoC system controller
156      provides an interface to override the native DWC SSI CS control.
157
158patternProperties:
159  "^.*@[0-9a-f]+$":
160    type: object
161    properties:
162      reg:
163        minimum: 0
164        maximum: 3
165
166unevaluatedProperties: false
167
168required:
169  - compatible
170  - reg
171  - "#address-cells"
172  - "#size-cells"
173  - clocks
174
175examples:
176  - |
177    spi@fff00000 {
178      compatible = "snps,dw-apb-ssi";
179      reg = <0xfff00000 0x1000>;
180      #address-cells = <1>;
181      #size-cells = <0>;
182      interrupts = <0 154 4>;
183      clocks = <&spi_m_clk>;
184      num-cs = <2>;
185      cs-gpios = <&gpio0 13 0>,
186                 <&gpio0 14 0>;
187      rx-sample-delay-ns = <3>;
188      flash@1 {
189        compatible = "spi-nand";
190        reg = <1>;
191        rx-sample-delay-ns = <7>;
192      };
193    };
194  - |
195    spi@1f040100 {
196      compatible = "baikal,bt1-sys-ssi";
197      reg = <0x1f040100 0x900>,
198            <0x1c000000 0x1000000>;
199      #address-cells = <1>;
200      #size-cells = <0>;
201      mux-controls = <&boot_mux>;
202      clocks = <&ccu_sys>;
203      clock-names = "ssi_clk";
204    };
205...
206