1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/spi/rockchip-sfc.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Rockchip Serial Flash Controller (SFC) 8 9maintainers: 10 - Heiko Stuebner <heiko@sntech.de> 11 - Chris Morgan <macromorgan@hotmail.com> 12 13allOf: 14 - $ref: spi-controller.yaml# 15 16properties: 17 compatible: 18 const: rockchip,sfc 19 description: 20 The rockchip sfc controller is a standalone IP with version register, 21 and the driver can handle all the feature difference inside the IP 22 depending on the version register. 23 24 reg: 25 maxItems: 1 26 27 interrupts: 28 maxItems: 1 29 30 clocks: 31 items: 32 - description: Bus Clock 33 - description: Module Clock 34 35 clock-names: 36 items: 37 - const: clk_sfc 38 - const: hclk_sfc 39 40 power-domains: 41 maxItems: 1 42 43 rockchip,sfc-no-dma: 44 description: Disable DMA and utilize FIFO mode only 45 type: boolean 46 47patternProperties: 48 "^flash@[0-3]$": 49 type: object 50 additionalProperties: true 51 52 properties: 53 reg: 54 minimum: 0 55 maximum: 3 56 57required: 58 - compatible 59 - reg 60 - interrupts 61 - clocks 62 - clock-names 63 64unevaluatedProperties: false 65 66examples: 67 - | 68 #include <dt-bindings/clock/px30-cru.h> 69 #include <dt-bindings/interrupt-controller/arm-gic.h> 70 #include <dt-bindings/power/px30-power.h> 71 72 sfc: spi@ff3a0000 { 73 compatible = "rockchip,sfc"; 74 reg = <0xff3a0000 0x4000>; 75 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 76 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 77 clock-names = "clk_sfc", "hclk_sfc"; 78 pinctrl-0 = <&sfc_clk &sfc_cs &sfc_bus2>; 79 pinctrl-names = "default"; 80 power-domains = <&power PX30_PD_MMC_NAND>; 81 #address-cells = <1>; 82 #size-cells = <0>; 83 84 flash@0 { 85 compatible = "jedec,spi-nor"; 86 reg = <0>; 87 spi-max-frequency = <108000000>; 88 spi-rx-bus-width = <2>; 89 spi-tx-bus-width = <2>; 90 }; 91 }; 92 93... 94