xref: /freebsd/sys/contrib/device-tree/Bindings/spi/renesas,rzv2m-csi.yaml (revision aa1a8ff2d6dbc51ef058f46f3db5a8bb77967145) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/spi/renesas,rzv2m-csi.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Renesas RZ/V2M Clocked Serial Interface (CSI)
8
9maintainers:
10  - Fabrizio Castro <fabrizio.castro.jz@renesas.com>
11  - Geert Uytterhoeven <geert+renesas@glider.be>
12
13allOf:
14  - $ref: spi-controller.yaml#
15
16properties:
17  compatible:
18    const: renesas,rzv2m-csi
19
20  reg:
21    maxItems: 1
22
23  interrupts:
24    maxItems: 1
25
26  clocks:
27    items:
28      - description: The clock used to generate the output clock (CSICLK)
29      - description: Internal clock to access the registers (PCLK)
30
31  clock-names:
32    items:
33      - const: csiclk
34      - const: pclk
35
36  resets:
37    maxItems: 1
38
39  power-domains:
40    maxItems: 1
41
42required:
43  - compatible
44  - reg
45  - interrupts
46  - clocks
47  - clock-names
48  - resets
49  - power-domains
50  - '#address-cells'
51  - '#size-cells'
52
53unevaluatedProperties: false
54
55examples:
56  - |
57    #include <dt-bindings/interrupt-controller/arm-gic.h>
58    #include <dt-bindings/clock/r9a09g011-cpg.h>
59    csi4: spi@a4020200 {
60        compatible = "renesas,rzv2m-csi";
61        reg = <0xa4020200 0x80>;
62        interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
63        clocks = <&cpg CPG_MOD R9A09G011_CSI4_CLK>,
64                 <&cpg CPG_MOD R9A09G011_CPERI_GRPH_PCLK>;
65        clock-names = "csiclk", "pclk";
66        resets = <&cpg R9A09G011_CSI_GPH_PRESETN>;
67        power-domains = <&cpg>;
68        #address-cells = <1>;
69        #size-cells = <0>;
70    };
71