1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/spi/renesas,rzv2m-csi.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Renesas RZ/V2M Clocked Serial Interface (CSI) 8 9maintainers: 10 - Fabrizio Castro <fabrizio.castro.jz@renesas.com> 11 - Geert Uytterhoeven <geert+renesas@glider.be> 12 13allOf: 14 - $ref: spi-controller.yaml# 15 16properties: 17 compatible: 18 const: renesas,rzv2m-csi 19 20 reg: 21 maxItems: 1 22 23 interrupts: 24 maxItems: 1 25 26 clocks: 27 items: 28 - description: The clock used to generate the output clock (CSICLK) 29 - description: Internal clock to access the registers (PCLK) 30 31 clock-names: 32 items: 33 - const: csiclk 34 - const: pclk 35 36 resets: 37 maxItems: 1 38 39 power-domains: 40 maxItems: 1 41 42 renesas,csi-no-ss: 43 type: boolean 44 description: 45 The CSI Slave Selection (SS) pin won't be used to enable transmission and 46 reception. Only available when in target mode. 47 48required: 49 - compatible 50 - reg 51 - interrupts 52 - clocks 53 - clock-names 54 - resets 55 - power-domains 56 - '#address-cells' 57 - '#size-cells' 58 59dependencies: 60 renesas,csi-no-ss: [ spi-slave ] 61 62unevaluatedProperties: false 63 64examples: 65 - | 66 #include <dt-bindings/interrupt-controller/arm-gic.h> 67 #include <dt-bindings/clock/r9a09g011-cpg.h> 68 csi4: spi@a4020200 { 69 compatible = "renesas,rzv2m-csi"; 70 reg = <0xa4020200 0x80>; 71 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; 72 clocks = <&cpg CPG_MOD R9A09G011_CSI4_CLK>, 73 <&cpg CPG_MOD R9A09G011_CPERI_GRPH_PCLK>; 74 clock-names = "csiclk", "pclk"; 75 resets = <&cpg R9A09G011_CSI_GPH_PRESETN>; 76 power-domains = <&cpg>; 77 #address-cells = <1>; 78 #size-cells = <0>; 79 }; 80