xref: /freebsd/sys/contrib/device-tree/Bindings/spi/qcom,spi-qcom-qspi.yaml (revision cb7aa33ac6cd46a5434798e50363136e64f3ae98) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/spi/qcom,spi-qcom-qspi.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Quad Serial Peripheral Interface (QSPI)
8
9maintainers:
10  - Bjorn Andersson <bjorn.andersson@linaro.org>
11
12description: The QSPI controller allows SPI protocol communication in single,
13  dual, or quad wire transmission modes for read/write access to slaves such
14  as NOR flash.
15
16allOf:
17  - $ref: /schemas/spi/spi-controller.yaml#
18
19properties:
20  compatible:
21    items:
22      - enum:
23          - qcom,sc7180-qspi
24          - qcom,sc7280-qspi
25          - qcom,sdm845-qspi
26
27      - const: qcom,qspi-v1
28
29  reg:
30    maxItems: 1
31
32  interrupts:
33    maxItems: 1
34
35  clock-names:
36    items:
37      - const: iface
38      - const: core
39
40  clocks:
41    items:
42      - description: AHB clock
43      - description: QSPI core clock
44
45  interconnects:
46    minItems: 1
47    maxItems: 2
48
49  interconnect-names:
50    minItems: 1
51    items:
52      - const: qspi-config
53      - const: qspi-memory
54
55  operating-points-v2: true
56
57  power-domains:
58    maxItems: 1
59
60required:
61  - compatible
62  - reg
63  - interrupts
64  - clock-names
65  - clocks
66
67unevaluatedProperties: false
68
69examples:
70  - |
71    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
72    #include <dt-bindings/interrupt-controller/arm-gic.h>
73
74    soc: soc {
75        #address-cells = <2>;
76        #size-cells = <2>;
77
78        qspi: spi@88df000 {
79            compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
80            reg = <0 0x88df000 0 0x600>;
81            #address-cells = <1>;
82            #size-cells = <0>;
83            interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
84            clock-names = "iface", "core";
85            clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
86                         <&gcc GCC_QSPI_CORE_CLK>;
87
88            flash@0 {
89                compatible = "jedec,spi-nor";
90                reg = <0>;
91                spi-max-frequency = <25000000>;
92                spi-tx-bus-width = <2>;
93                spi-rx-bus-width = <2>;
94            };
95        };
96    };
97...
98