xref: /freebsd/sys/contrib/device-tree/Bindings/spi/mediatek,spi-mtk-nor.yaml (revision 994297b01b98816bea1abf45ae4bac1bc69ee7a0) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/spi/mediatek,spi-mtk-nor.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Serial NOR flash controller for MediaTek ARM SoCs
8
9maintainers:
10  - Bayi Cheng <bayi.cheng@mediatek.com>
11  - Chuanhong Guo <gch981213@gmail.com>
12
13description: |
14  This spi controller support single, dual, or quad mode transfer for
15  SPI NOR flash. There should be only one spi slave device following
16  generic spi bindings. It's not recommended to use this controller
17  for devices other than SPI NOR flash due to limited transfer
18  capability of this controller.
19
20allOf:
21  - $ref: /spi/spi-controller.yaml#
22
23properties:
24  compatible:
25    oneOf:
26      - items:
27          - enum:
28              - mediatek,mt2701-nor
29              - mediatek,mt2712-nor
30              - mediatek,mt7622-nor
31              - mediatek,mt7623-nor
32              - mediatek,mt7629-nor
33              - mediatek,mt8192-nor
34              - mediatek,mt8195-nor
35          - enum:
36              - mediatek,mt8173-nor
37      - items:
38          - const: mediatek,mt8173-nor
39  reg:
40    maxItems: 1
41
42  interrupts:
43    maxItems: 1
44
45  clocks:
46    items:
47      - description: clock used for spi bus
48      - description: clock used for controller
49
50  clock-names:
51    items:
52      - const: spi
53      - const: sf
54
55required:
56  - compatible
57  - reg
58  - interrupts
59  - clocks
60  - clock-names
61
62unevaluatedProperties: false
63
64examples:
65  - |
66    #include <dt-bindings/clock/mt8173-clk.h>
67
68    soc {
69      #address-cells = <2>;
70      #size-cells = <2>;
71
72      nor_flash: spi@1100d000 {
73        compatible = "mediatek,mt8173-nor";
74        reg = <0 0x1100d000 0 0xe0>;
75        interrupts = <&spi_flash_irq>;
76        clocks = <&pericfg CLK_PERI_SPI>, <&topckgen CLK_TOP_SPINFI_IFR_SEL>;
77        clock-names = "spi", "sf";
78        #address-cells = <1>;
79        #size-cells = <0>;
80
81        flash@0 {
82          compatible = "jedec,spi-nor";
83          reg = <0>;
84        };
85      };
86    };
87
88