1* SPI (Serial Peripheral Interface) 2 3Required properties: 4- cell-index : QE SPI subblock index. 5 0: QE subblock SPI1 6 1: QE subblock SPI2 7- compatible : should be "fsl,spi" or "aeroflexgaisler,spictrl". 8- mode : the SPI operation mode, it can be "cpu" or "cpu-qe". 9- reg : Offset and length of the register set for the device 10- interrupts : <a b> where a is the interrupt number and b is a 11 field that represents an encoding of the sense and level 12 information for the interrupt. This should be encoded based on 13 the information in section 2) depending on the type of interrupt 14 controller you have. 15- clock-frequency : input clock frequency to non FSL_SOC cores 16 17Optional properties: 18- cs-gpios : specifies the gpio pins to be used for chipselects. 19 The gpios will be referred to as reg = <index> in the SPI child nodes. 20 If unspecified, a single SPI device without a chip select can be used. 21- fsl,spisel_boot : for the MPC8306 and MPC8309, specifies that the 22 SPISEL_BOOT signal is used as chip select for a slave device. Use 23 reg = <number of gpios> in the corresponding child node, i.e. 0 if 24 the cs-gpios property is not present. 25 26Example: 27 spi@4c0 { 28 cell-index = <0>; 29 compatible = "fsl,spi"; 30 reg = <4c0 40>; 31 interrupts = <82 0>; 32 interrupt-parent = <700>; 33 mode = "cpu"; 34 cs-gpios = <&gpio 18 1 // device reg=<0> 35 &gpio 19 1>; // device reg=<1> 36 }; 37 38 39* eSPI (Enhanced Serial Peripheral Interface) 40 41Required properties: 42- compatible : should be "fsl,mpc8536-espi". 43- reg : Offset and length of the register set for the device. 44- interrupts : should contain eSPI interrupt, the device has one interrupt. 45- fsl,espi-num-chipselects : the number of the chipselect signals. 46 47Optional properties: 48- fsl,csbef: chip select assertion time in bits before frame starts 49- fsl,csaft: chip select negation time in bits after frame ends 50 51Example: 52 spi@110000 { 53 #address-cells = <1>; 54 #size-cells = <0>; 55 compatible = "fsl,mpc8536-espi"; 56 reg = <0x110000 0x1000>; 57 interrupts = <53 0x2>; 58 interrupt-parent = <&mpic>; 59 fsl,espi-num-chipselects = <4>; 60 fsl,csbef = <1>; 61 fsl,csaft = <1>; 62 }; 63