1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/spi/brcm,spi-bcm-qspi.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Broadcom SPI controller 8 9maintainers: 10 - Kamal Dasu <kdasu.kdev@gmail.com> 11 - Rafał Miłecki <rafal@milecki.pl> 12 13description: | 14 The Broadcom SPI controller is a SPI master found on various SOCs, including 15 BRCMSTB (BCM7XXX), Cygnus, NSP and NS2. The Broadcom Master SPI hw IP consits 16 of: 17 MSPI : SPI master controller can read and write to a SPI slave device 18 BSPI : Broadcom SPI in combination with the MSPI hw IP provides acceleration 19 for flash reads and be configured to do single, double, quad lane 20 io with 3-byte and 4-byte addressing support. 21 22 Supported Broadcom SoCs have one instance of MSPI+BSPI controller IP. 23 MSPI master can be used wihout BSPI. BRCMSTB SoCs have an additional instance 24 of a MSPI master without the BSPI to use with non flash slave devices that 25 use SPI protocol. 26 27allOf: 28 - $ref: spi-controller.yaml# 29 30properties: 31 compatible: 32 oneOf: 33 - description: Second Instance of MSPI BRCMSTB SoCs 34 items: 35 - enum: 36 - brcm,spi-bcm7425-qspi 37 - brcm,spi-bcm7429-qspi 38 - brcm,spi-bcm7435-qspi 39 - brcm,spi-bcm7445-qspi 40 - brcm,spi-bcm7216-qspi 41 - brcm,spi-bcm7278-qspi 42 - const: brcm,spi-bcm-qspi 43 - const: brcm,spi-brcmstb-mspi 44 - description: Second Instance of MSPI BRCMSTB SoCs 45 items: 46 - enum: 47 - brcm,spi-brcmstb-qspi 48 - brcm,spi-brcmstb-mspi 49 - brcm,spi-nsp-qspi 50 - brcm,spi-ns2-qspi 51 - const: brcm,spi-bcm-qspi 52 53 reg: 54 minItems: 1 55 maxItems: 5 56 57 reg-names: 58 minItems: 1 59 maxItems: 5 60 items: 61 - const: mspi 62 - const: bspi 63 - enum: [ intr_regs, intr_status_reg, cs_reg ] 64 - enum: [ intr_regs, intr_status_reg, cs_reg ] 65 - enum: [ intr_regs, intr_status_reg, cs_reg ] 66 67 interrupts: 68 minItems: 1 69 maxItems: 7 70 71 interrupt-names: 72 oneOf: 73 - minItems: 1 74 maxItems: 7 75 items: 76 - const: mspi_done 77 - const: mspi_halted 78 - const: spi_lr_fullness_reached 79 - const: spi_lr_session_aborted 80 - const: spi_lr_impatient 81 - const: spi_lr_session_done 82 - const: spi_lr_overread 83 - const: spi_l1_intr 84 85 clocks: 86 maxItems: 1 87 description: reference clock for this block 88 89 native-endian: 90 $ref: /schemas/types.yaml#/definitions/flag 91 description: Defined when using BE SoC and device uses BE register read/write 92 93unevaluatedProperties: false 94 95required: 96 - reg 97 - reg-names 98 - interrupts 99 - interrupt-names 100 101examples: 102 - | # BRCMSTB SoC: SPI Master (MSPI+BSPI) for SPI-NOR access 103 spi@f03e3400 { 104 compatible = "brcm,spi-brcmstb-qspi", "brcm,spi-bcm-qspi"; 105 reg = <0xf03e3400 0x188>, <0xf03e3200 0x50>, <0xf03e0920 0x4>; 106 reg-names = "mspi", "bspi", "cs_reg"; 107 interrupts = <0x5>, <0x6>, <0x1>, <0x2>, <0x3>, <0x4>, <0x0>; 108 interrupt-parent = <&gic>; 109 interrupt-names = "mspi_done", 110 "mspi_halted", 111 "spi_lr_fullness_reached", 112 "spi_lr_session_aborted", 113 "spi_lr_impatient", 114 "spi_lr_session_done", 115 "spi_lr_overread"; 116 clocks = <&hif_spi>; 117 #address-cells = <0x1>; 118 #size-cells = <0x0>; 119 120 flash@0 { 121 #size-cells = <0x2>; 122 #address-cells = <0x2>; 123 compatible = "m25p80"; 124 reg = <0x0>; 125 spi-max-frequency = <0x2625a00>; 126 spi-cpol; 127 spi-cpha; 128 }; 129 }; 130 - | # BRCMSTB SoC: MSPI master for any SPI device 131 spi@f0416000 { 132 clocks = <&upg_fixed>; 133 compatible = "brcm,spi-brcmstb-mspi", "brcm,spi-bcm-qspi"; 134 reg = <0xf0416000 0x180>; 135 reg-names = "mspi"; 136 interrupts = <0x14>; 137 interrupt-parent = <&irq0_aon_intc>; 138 interrupt-names = "mspi_done"; 139 #address-cells = <1>; 140 #size-cells = <0>; 141 }; 142 - | # iProc SoC 143 #include <dt-bindings/interrupt-controller/irq.h> 144 #include <dt-bindings/interrupt-controller/arm-gic.h> 145 146 spi@18027200 { 147 compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi"; 148 reg = <0x18027200 0x184>, 149 <0x18027000 0x124>, 150 <0x1811c408 0x004>, 151 <0x180273a0 0x01c>; 152 reg-names = "mspi", "bspi", "intr_regs", "intr_status_reg"; 153 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 154 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 155 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 156 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 157 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 158 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 159 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 160 interrupt-names = "mspi_done", 161 "mspi_halted", 162 "spi_lr_fullness_reached", 163 "spi_lr_session_aborted", 164 "spi_lr_impatient", 165 "spi_lr_session_done"; 166 clocks = <&iprocmed>; 167 num-cs = <2>; 168 #address-cells = <1>; 169 #size-cells = <0>; 170 }; 171 - | # NS2 SoC 172 #include <dt-bindings/interrupt-controller/irq.h> 173 #include <dt-bindings/interrupt-controller/arm-gic.h> 174 175 spi@66470200 { 176 compatible = "brcm,spi-ns2-qspi", "brcm,spi-bcm-qspi"; 177 reg = <0x66470200 0x184>, 178 <0x66470000 0x124>, 179 <0x67017408 0x004>, 180 <0x664703a0 0x01c>; 181 reg-names = "mspi", "bspi", "intr_regs", "intr_status_reg"; 182 interrupts = <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>; 183 interrupt-names = "spi_l1_intr"; 184 clocks = <&iprocmed>; 185 num-cs = <2>; 186 #address-cells = <1>; 187 #size-cells = <0>; 188 189 flash@0 { 190 #address-cells = <1>; 191 #size-cells = <1>; 192 compatible = "m25p80"; 193 reg = <0x0>; 194 spi-max-frequency = <12500000>; 195 spi-cpol; 196 spi-cpha; 197 }; 198 }; 199