1Broadcom SPI controller 2 3The Broadcom SPI controller is a SPI master found on various SOCs, including 4BRCMSTB (BCM7XXX), Cygnus, NSP and NS2. The Broadcom Master SPI hw IP consits 5of : 6 MSPI : SPI master controller can read and write to a SPI slave device 7 BSPI : Broadcom SPI in combination with the MSPI hw IP provides acceleration 8 for flash reads and be configured to do single, double, quad lane 9 io with 3-byte and 4-byte addressing support. 10 11 Supported Broadcom SoCs have one instance of MSPI+BSPI controller IP. 12 MSPI master can be used wihout BSPI. BRCMSTB SoCs have an additional instance 13 of a MSPI master without the BSPI to use with non flash slave devices that 14 use SPI protocol. 15 16Required properties: 17 18- #address-cells: 19 Must be <1>, as required by generic SPI binding. 20 21- #size-cells: 22 Must be <0>, also as required by generic SPI binding. 23 24- compatible: 25 Must be one of : 26 "brcm,spi-brcmstb-qspi", "brcm,spi-bcm-qspi" : MSPI+BSPI on BRCMSTB SoCs 27 "brcm,spi-brcmstb-mspi", "brcm,spi-bcm-qspi" : Second Instance of MSPI 28 BRCMSTB SoCs 29 "brcm,spi-bcm7425-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI 30 BRCMSTB SoCs 31 "brcm,spi-bcm7429-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI 32 BRCMSTB SoCs 33 "brcm,spi-bcm7435-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI 34 BRCMSTB SoCs 35 "brcm,spi-bcm7445-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI 36 BRCMSTB SoCs 37 "brcm,spi-bcm7216-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI 38 BRCMSTB SoCs 39 "brcm,spi-bcm7278-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI 40 BRCMSTB SoCs 41 "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi" : MSPI+BSPI on Cygnus, NSP 42 "brcm,spi-ns2-qspi", "brcm,spi-bcm-qspi" : NS2 SoCs 43 44- reg: 45 Define the bases and ranges of the associated I/O address spaces. 46 The required range is MSPI controller registers. 47 48- reg-names: 49 First name does not matter, but must be reserved for the MSPI controller 50 register range as mentioned in 'reg' above, and will typically contain 51 - "bspi_regs": BSPI register range, not required with compatible 52 "spi-brcmstb-mspi" 53 - "mspi_regs": MSPI register range is required for compatible strings 54 - "intr_regs", "intr_status_reg" : Interrupt and status register for 55 NSP, NS2, Cygnus SoC 56 57- interrupts 58 The interrupts used by the MSPI and/or BSPI controller. 59 60- interrupt-names: 61 Names of interrupts associated with MSPI 62 - "mspi_halted" : 63 - "mspi_done": Indicates that the requested SPI operation is complete. 64 - "spi_lr_fullness_reached" : Linear read BSPI pipe full 65 - "spi_lr_session_aborted" : Linear read BSPI pipe aborted 66 - "spi_lr_impatient" : Linear read BSPI requested when pipe empty 67 - "spi_lr_session_done" : Linear read BSPI session done 68 69- clocks: 70 A phandle to the reference clock for this block. 71 72Optional properties: 73 74 75- native-endian 76 Defined when using BE SoC and device uses BE register read/write 77 78Recommended optional m25p80 properties: 79- spi-rx-bus-width: Definition as per 80 Documentation/devicetree/bindings/spi/spi-bus.txt 81 82Examples: 83 84BRCMSTB SoC Example: 85 86 SPI Master (MSPI+BSPI) for SPI-NOR access: 87 88 spi@f03e3400 { 89 #address-cells = <0x1>; 90 #size-cells = <0x0>; 91 compatible = "brcm,spi-brcmstb-qspi", "brcm,spi-bcm-qspi"; 92 reg = <0xf03e0920 0x4 0xf03e3400 0x188 0xf03e3200 0x50>; 93 reg-names = "cs_reg", "mspi", "bspi"; 94 interrupts = <0x6 0x5 0x4 0x3 0x2 0x1 0x0>; 95 interrupt-parent = <0x1c>; 96 interrupt-names = "mspi_halted", 97 "mspi_done", 98 "spi_lr_overread", 99 "spi_lr_session_done", 100 "spi_lr_impatient", 101 "spi_lr_session_aborted", 102 "spi_lr_fullness_reached"; 103 104 clocks = <&hif_spi>; 105 clock-names = "sw_spi"; 106 107 m25p80@0 { 108 #size-cells = <0x2>; 109 #address-cells = <0x2>; 110 compatible = "m25p80"; 111 reg = <0x0>; 112 spi-max-frequency = <0x2625a00>; 113 spi-cpol; 114 spi-cpha; 115 m25p,fast-read; 116 117 flash0.bolt@0 { 118 reg = <0x0 0x0 0x0 0x100000>; 119 }; 120 121 flash0.macadr@100000 { 122 reg = <0x0 0x100000 0x0 0x10000>; 123 }; 124 125 flash0.nvram@110000 { 126 reg = <0x0 0x110000 0x0 0x10000>; 127 }; 128 129 flash0.kernel@120000 { 130 reg = <0x0 0x120000 0x0 0x400000>; 131 }; 132 133 flash0.devtree@520000 { 134 reg = <0x0 0x520000 0x0 0x10000>; 135 }; 136 137 flash0.splash@530000 { 138 reg = <0x0 0x530000 0x0 0x80000>; 139 }; 140 141 flash0@0 { 142 reg = <0x0 0x0 0x0 0x4000000>; 143 }; 144 }; 145 }; 146 147 148 MSPI master for any SPI device : 149 150 spi@f0416000 { 151 #address-cells = <1>; 152 #size-cells = <0>; 153 clocks = <&upg_fixed>; 154 compatible = "brcm,spi-brcmstb-mspi", "brcm,spi-bcm-qspi"; 155 reg = <0xf0416000 0x180>; 156 reg-names = "mspi"; 157 interrupts = <0x14>; 158 interrupt-parent = <&irq0_aon_intc>; 159 interrupt-names = "mspi_done"; 160 }; 161 162iProc SoC Example: 163 164 qspi: spi@18027200 { 165 compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi"; 166 reg = <0x18027200 0x184>, 167 <0x18027000 0x124>, 168 <0x1811c408 0x004>, 169 <0x180273a0 0x01c>; 170 reg-names = "mspi_regs", "bspi_regs", "intr_regs", "intr_status_reg"; 171 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 172 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 173 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 174 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 175 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 176 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 177 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 178 interrupt-names = 179 "spi_lr_fullness_reached", 180 "spi_lr_session_aborted", 181 "spi_lr_impatient", 182 "spi_lr_session_done", 183 "mspi_done", 184 "mspi_halted"; 185 clocks = <&iprocmed>; 186 clock-names = "iprocmed"; 187 num-cs = <2>; 188 #address-cells = <1>; 189 #size-cells = <0>; 190 }; 191 192 193 NS2 SoC Example: 194 195 qspi: spi@66470200 { 196 compatible = "brcm,spi-ns2-qspi", "brcm,spi-bcm-qspi"; 197 reg = <0x66470200 0x184>, 198 <0x66470000 0x124>, 199 <0x67017408 0x004>, 200 <0x664703a0 0x01c>; 201 reg-names = "mspi", "bspi", "intr_regs", 202 "intr_status_reg"; 203 interrupts = <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>; 204 interrupt-names = "spi_l1_intr"; 205 clocks = <&iprocmed>; 206 clock-names = "iprocmed"; 207 num-cs = <2>; 208 #address-cells = <1>; 209 #size-cells = <0>; 210 }; 211 212 213 m25p80 node for NSP, NS2 214 215 &qspi { 216 flash: m25p80@0 { 217 #address-cells = <1>; 218 #size-cells = <1>; 219 compatible = "m25p80"; 220 reg = <0x0>; 221 spi-max-frequency = <12500000>; 222 m25p,fast-read; 223 spi-cpol; 224 spi-cpha; 225 226 partition@0 { 227 label = "boot"; 228 reg = <0x00000000 0x000a0000>; 229 }; 230 231 partition@a0000 { 232 label = "env"; 233 reg = <0x000a0000 0x00060000>; 234 }; 235 236 partition@100000 { 237 label = "system"; 238 reg = <0x00100000 0x00600000>; 239 }; 240 241 partition@700000 { 242 label = "rootfs"; 243 reg = <0x00700000 0x01900000>; 244 }; 245 }; 246