1Broadcom SPI controller 2 3The Broadcom SPI controller is a SPI master found on various SOCs, including 4BRCMSTB (BCM7XXX), Cygnus, NSP and NS2. The Broadcom Master SPI hw IP consits 5of : 6 MSPI : SPI master controller can read and write to a SPI slave device 7 BSPI : Broadcom SPI in combination with the MSPI hw IP provides acceleration 8 for flash reads and be configured to do single, double, quad lane 9 io with 3-byte and 4-byte addressing support. 10 11 Supported Broadcom SoCs have one instance of MSPI+BSPI controller IP. 12 MSPI master can be used wihout BSPI. BRCMSTB SoCs have an additional instance 13 of a MSPI master without the BSPI to use with non flash slave devices that 14 use SPI protocol. 15 16Required properties: 17 18- #address-cells: 19 Must be <1>, as required by generic SPI binding. 20 21- #size-cells: 22 Must be <0>, also as required by generic SPI binding. 23 24- compatible: 25 Must be one of : 26 "brcm,spi-brcmstb-qspi", "brcm,spi-bcm-qspi" : MSPI+BSPI on BRCMSTB SoCs 27 "brcm,spi-brcmstb-mspi", "brcm,spi-bcm-qspi" : Second Instance of MSPI 28 BRCMSTB SoCs 29 "brcm,spi-bcm7425-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI 30 BRCMSTB SoCs 31 "brcm,spi-bcm7429-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI 32 BRCMSTB SoCs 33 "brcm,spi-bcm7435-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI 34 BRCMSTB SoCs 35 "brcm,spi-bcm7216-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI 36 BRCMSTB SoCs 37 "brcm,spi-bcm7278-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI 38 BRCMSTB SoCs 39 "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi" : MSPI+BSPI on Cygnus, NSP 40 "brcm,spi-ns2-qspi", "brcm,spi-bcm-qspi" : NS2 SoCs 41 42- reg: 43 Define the bases and ranges of the associated I/O address spaces. 44 The required range is MSPI controller registers. 45 46- reg-names: 47 First name does not matter, but must be reserved for the MSPI controller 48 register range as mentioned in 'reg' above, and will typically contain 49 - "bspi_regs": BSPI register range, not required with compatible 50 "spi-brcmstb-mspi" 51 - "mspi_regs": MSPI register range is required for compatible strings 52 - "intr_regs", "intr_status_reg" : Interrupt and status register for 53 NSP, NS2, Cygnus SoC 54 55- interrupts 56 The interrupts used by the MSPI and/or BSPI controller. 57 58- interrupt-names: 59 Names of interrupts associated with MSPI 60 - "mspi_halted" : 61 - "mspi_done": Indicates that the requested SPI operation is complete. 62 - "spi_lr_fullness_reached" : Linear read BSPI pipe full 63 - "spi_lr_session_aborted" : Linear read BSPI pipe aborted 64 - "spi_lr_impatient" : Linear read BSPI requested when pipe empty 65 - "spi_lr_session_done" : Linear read BSPI session done 66 67- clocks: 68 A phandle to the reference clock for this block. 69 70Optional properties: 71 72 73- native-endian 74 Defined when using BE SoC and device uses BE register read/write 75 76Recommended optional m25p80 properties: 77- spi-rx-bus-width: Definition as per 78 Documentation/devicetree/bindings/spi/spi-bus.txt 79 80Examples: 81 82BRCMSTB SoC Example: 83 84 SPI Master (MSPI+BSPI) for SPI-NOR access: 85 86 spi@f03e3400 { 87 #address-cells = <0x1>; 88 #size-cells = <0x0>; 89 compatible = "brcm,spi-brcmstb-qspi", "brcm,spi-bcm-qspi"; 90 reg = <0xf03e0920 0x4 0xf03e3400 0x188 0xf03e3200 0x50>; 91 reg-names = "cs_reg", "mspi", "bspi"; 92 interrupts = <0x6 0x5 0x4 0x3 0x2 0x1 0x0>; 93 interrupt-parent = <0x1c>; 94 interrupt-names = "mspi_halted", 95 "mspi_done", 96 "spi_lr_overread", 97 "spi_lr_session_done", 98 "spi_lr_impatient", 99 "spi_lr_session_aborted", 100 "spi_lr_fullness_reached"; 101 102 clocks = <&hif_spi>; 103 clock-names = "sw_spi"; 104 105 m25p80@0 { 106 #size-cells = <0x2>; 107 #address-cells = <0x2>; 108 compatible = "m25p80"; 109 reg = <0x0>; 110 spi-max-frequency = <0x2625a00>; 111 spi-cpol; 112 spi-cpha; 113 m25p,fast-read; 114 115 flash0.bolt@0 { 116 reg = <0x0 0x0 0x0 0x100000>; 117 }; 118 119 flash0.macadr@100000 { 120 reg = <0x0 0x100000 0x0 0x10000>; 121 }; 122 123 flash0.nvram@110000 { 124 reg = <0x0 0x110000 0x0 0x10000>; 125 }; 126 127 flash0.kernel@120000 { 128 reg = <0x0 0x120000 0x0 0x400000>; 129 }; 130 131 flash0.devtree@520000 { 132 reg = <0x0 0x520000 0x0 0x10000>; 133 }; 134 135 flash0.splash@530000 { 136 reg = <0x0 0x530000 0x0 0x80000>; 137 }; 138 139 flash0@0 { 140 reg = <0x0 0x0 0x0 0x4000000>; 141 }; 142 }; 143 }; 144 145 146 MSPI master for any SPI device : 147 148 spi@f0416000 { 149 #address-cells = <1>; 150 #size-cells = <0>; 151 clocks = <&upg_fixed>; 152 compatible = "brcm,spi-brcmstb-mspi", "brcm,spi-bcm-qspi"; 153 reg = <0xf0416000 0x180>; 154 reg-names = "mspi"; 155 interrupts = <0x14>; 156 interrupt-parent = <&irq0_aon_intc>; 157 interrupt-names = "mspi_done"; 158 }; 159 160iProc SoC Example: 161 162 qspi: spi@18027200 { 163 compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi"; 164 reg = <0x18027200 0x184>, 165 <0x18027000 0x124>, 166 <0x1811c408 0x004>, 167 <0x180273a0 0x01c>; 168 reg-names = "mspi_regs", "bspi_regs", "intr_regs", "intr_status_reg"; 169 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 170 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 171 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 172 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 173 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 174 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 175 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 176 interrupt-names = 177 "spi_lr_fullness_reached", 178 "spi_lr_session_aborted", 179 "spi_lr_impatient", 180 "spi_lr_session_done", 181 "mspi_done", 182 "mspi_halted"; 183 clocks = <&iprocmed>; 184 clock-names = "iprocmed"; 185 num-cs = <2>; 186 #address-cells = <1>; 187 #size-cells = <0>; 188 }; 189 190 191 NS2 SoC Example: 192 193 qspi: spi@66470200 { 194 compatible = "brcm,spi-ns2-qspi", "brcm,spi-bcm-qspi"; 195 reg = <0x66470200 0x184>, 196 <0x66470000 0x124>, 197 <0x67017408 0x004>, 198 <0x664703a0 0x01c>; 199 reg-names = "mspi", "bspi", "intr_regs", 200 "intr_status_reg"; 201 interrupts = <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>; 202 interrupt-names = "spi_l1_intr"; 203 clocks = <&iprocmed>; 204 clock-names = "iprocmed"; 205 num-cs = <2>; 206 #address-cells = <1>; 207 #size-cells = <0>; 208 }; 209 210 211 m25p80 node for NSP, NS2 212 213 &qspi { 214 flash: m25p80@0 { 215 #address-cells = <1>; 216 #size-cells = <1>; 217 compatible = "m25p80"; 218 reg = <0x0>; 219 spi-max-frequency = <12500000>; 220 m25p,fast-read; 221 spi-cpol; 222 spi-cpha; 223 224 partition@0 { 225 label = "boot"; 226 reg = <0x00000000 0x000a0000>; 227 }; 228 229 partition@a0000 { 230 label = "env"; 231 reg = <0x000a0000 0x00060000>; 232 }; 233 234 partition@100000 { 235 label = "system"; 236 reg = <0x00100000 0x00600000>; 237 }; 238 239 partition@700000 { 240 label = "rootfs"; 241 reg = <0x00700000 0x01900000>; 242 }; 243 }; 244