xref: /freebsd/sys/contrib/device-tree/Bindings/spi/atmel,at91rm9200-spi.yaml (revision af23369a6deaaeb612ab266eb88b8bb8d560c322) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2# Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/spi/atmel,at91rm9200-spi.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: Atmel SPI device
9
10maintainers:
11  - Tudor Ambarus <tudor.ambarus@microchip.com>
12
13allOf:
14  - $ref: spi-controller.yaml#
15
16properties:
17  compatible:
18    oneOf:
19      - const: atmel,at91rm9200-spi
20      - items:
21          - const: microchip,sam9x60-spi
22          - const: atmel,at91rm9200-spi
23
24  reg:
25    maxItems: 1
26
27  interrupts:
28    maxItems: 1
29
30  clock-names:
31    contains:
32      const: spi_clk
33
34  clocks:
35    maxItems: 1
36
37  atmel,fifo-size:
38    $ref: /schemas/types.yaml#/definitions/uint32
39    description: |
40      Maximum number of data the RX and TX FIFOs can store for FIFO
41      capable SPI controllers.
42    enum: [ 16, 32 ]
43
44required:
45  - compatible
46  - reg
47  - interrupts
48  - clock-names
49  - clocks
50
51unevaluatedProperties: false
52
53examples:
54  - |
55    #include <dt-bindings/gpio/gpio.h>
56    #include <dt-bindings/interrupt-controller/irq.h>
57
58    spi1: spi@fffcc000 {
59        compatible = "atmel,at91rm9200-spi";
60        reg = <0xfffcc000 0x4000>;
61        interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>;
62        #address-cells = <1>;
63        #size-cells = <0>;
64        clocks = <&spi1_clk>;
65        clock-names = "spi_clk";
66        cs-gpios = <&pioB 3 GPIO_ACTIVE_HIGH>;
67        atmel,fifo-size = <32>;
68
69        mmc@0 {
70            compatible = "mmc-spi-slot";
71            reg = <0>;
72            gpios = <&pioC 4 GPIO_ACTIVE_HIGH>;    /* CD */
73            spi-max-frequency = <25000000>;
74        };
75    };
76