1Device-Tree bindings for Xilinx SPDIF IP 2 3The IP supports playback and capture of SPDIF audio 4 5Required properties: 6 - compatible: "xlnx,spdif-2.0" 7 - clock-names: List of input clocks. 8 Required elements: "s_axi_aclk", "aud_clk_i" 9 - clocks: Input clock specifier. Refer to common clock bindings. 10 - reg: Base address and address length of the IP core instance. 11 - interrupts-parent: Phandle for interrupt controller. 12 - interrupts: List of Interrupt numbers. 13 - xlnx,spdif-mode: 0 :- receiver mode 14 1 :- transmitter mode 15 - xlnx,aud_clk_i: input audio clock value. 16 17Example: 18 spdif_0: spdif@80010000 { 19 clock-names = "aud_clk_i", "s_axi_aclk"; 20 clocks = <&misc_clk_0>, <&clk 71>; 21 compatible = "xlnx,spdif-2.0"; 22 interrupt-names = "spdif_interrupt"; 23 interrupt-parent = <&gic>; 24 interrupts = <0 91 4>; 25 reg = <0x0 0x80010000 0x0 0x10000>; 26 xlnx,spdif-mode = <1>; 27 xlnx,aud_clk_i = <49152913>; 28 }; 29