1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/sound/ti,tlv320adc3xxx.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Texas Instruments TLV320ADC3001/TLV320ADC3101 Stereo ADC 8 9maintainers: 10 - Ricard Wanderlof <ricardw@axis.com> 11 12description: | 13 Texas Instruments TLV320ADC3001 and TLV320ADC3101 Stereo ADC 14 https://www.ti.com/product/TLV320ADC3001 15 https://www.ti.com/product/TLV320ADC3101 16 17allOf: 18 - $ref: dai-common.yaml# 19 20properties: 21 compatible: 22 enum: 23 - ti,tlv320adc3001 24 - ti,tlv320adc3101 25 26 reg: 27 maxItems: 1 28 description: I2C address 29 30 '#sound-dai-cells': 31 const: 0 32 33 '#gpio-cells': 34 const: 2 35 36 gpio-controller: true 37 38 reset-gpios: 39 maxItems: 1 40 description: GPIO pin used for codec reset (RESET pin) 41 42 clocks: 43 maxItems: 1 44 description: Master clock (MCLK) 45 46 ti,dmdin-gpio1: 47 $ref: /schemas/types.yaml#/definitions/uint32 48 enum: 49 - 0 # ADC3XXX_GPIO_DISABLED - I/O buffers powered down and not used 50 - 1 # ADC3XXX_GPIO_INPUT - Various non-GPIO input functions 51 - 2 # ADC3XXX_GPIO_GPI - General purpose input 52 - 3 # ADC3XXX_GPIO_GPO - General purpose output 53 - 4 # ADC3XXX_GPIO_CLKOUT - Clock source set in CLKOUT_MUX reg 54 - 5 # ADC3XXX_GPIO_INT1 - INT1 output 55 - 6 # ADC3XXX_GPIO_SECONDARY_BCLK - Codec interface secondary BCLK 56 - 7 # ADC3XXX_GPIO_SECONDARY_WCLK - Codec interface secondary WCLK 57 default: 0 58 description: | 59 Configuration for DMDIN/GPIO1 pin. 60 61 When ADC3XXX_GPIO_GPO is configured, this causes corresponding the 62 ALSA control "GPIOx Output" to appear, as a switch control. 63 64 ti,dmclk-gpio2: 65 $ref: /schemas/types.yaml#/definitions/uint32 66 enum: 67 - 0 # ADC3XXX_GPIO_DISABLED - I/O buffers powered down and not used 68 - 1 # ADC3XXX_GPIO_INPUT - Various non-GPIO input functions 69 - 2 # ADC3XXX_GPIO_GPI - General purpose input 70 - 3 # ADC3XXX_GPIO_GPO - General purpose output 71 - 4 # ADC3XXX_GPIO_CLKOUT - Clock source set in CLKOUT_MUX reg 72 - 5 # ADC3XXX_GPIO_INT1 - INT1 output 73 - 6 # ADC3XXX_GPIO_SECONDARY_BCLK - Codec interface secondary BCLK 74 - 7 # ADC3XXX_GPIO_SECONDARY_WCLK - Codec interface secondary WCLK 75 default: 0 76 description: | 77 Configuration for DMCLK/GPIO2 pin. 78 79 When ADC3XXX_GPIO_GPO is configured, this causes corresponding the 80 ALSA control "GPIOx Output" to appear, as a switch control. 81 82 Note that there is currently no support for reading the GPIO pins as 83 inputs. 84 85 ti,micbias1-vg: 86 $ref: /schemas/types.yaml#/definitions/uint32 87 enum: 88 - 0 # ADC3XXX_MICBIAS_OFF - Mic bias is powered down 89 - 1 # ADC3XXX_MICBIAS_2_0V - Mic bias is set to 2.0V 90 - 2 # ADC3XXX_MICBIAS_2_5V - Mic bias is set to 2.5V 91 - 3 # ADC3XXX_MICBIAS_AVDD - Mic bias is same as AVDD supply 92 default: 0 93 description: | 94 Mic bias voltage output on MICBIAS1 pin 95 96 ti,micbias2-vg: 97 $ref: /schemas/types.yaml#/definitions/uint32 98 enum: 99 - 0 # ADC3XXX_MICBIAS_OFF - Mic bias is powered down 100 - 1 # ADC3XXX_MICBIAS_2_0V - Mic bias is set to 2.0V 101 - 2 # ADC3XXX_MICBIAS_2_5V - Mic bias is set to 2.5V 102 - 3 # ADC3XXX_MICBIAS_AVDD - Mic bias is same as AVDD supply 103 default: 0 104 description: | 105 Mic bias voltage output on MICBIAS2 pin 106 107required: 108 - compatible 109 - reg 110 - clocks 111 112unevaluatedProperties: false 113 114examples: 115 - | 116 117 #include <dt-bindings/gpio/gpio.h> 118 #include <dt-bindings/sound/tlv320adc3xxx.h> 119 120 i2c { 121 #address-cells = <1>; 122 #size-cells = <0>; 123 tlv320adc3101: audio-codec@18 { 124 compatible = "ti,tlv320adc3101"; 125 reg = <0x18>; 126 reset-gpios = <&gpio_pc 3 GPIO_ACTIVE_LOW>; 127 clocks = <&audio_mclk>; 128 gpio-controller; 129 #gpio-cells = <2>; 130 ti,dmdin-gpio1 = <ADC3XXX_GPIO_GPO>; 131 ti,micbias1-vg = <ADC3XXX_MICBIAS_AVDD>; 132 }; 133 }; 134 135 audio_mclk: clock { 136 compatible = "fixed-clock"; 137 #clock-cells = <0>; 138 clock-frequency = <24576000>; 139 }; 140... 141