1STMicroelectronics STM32 Serial Audio Interface (SAI). 2 3The SAI interface (Serial Audio Interface) offers a wide set of audio protocols 4as I2S standards, LSB or MSB-justified, PCM/DSP, TDM, and AC'97. 5The SAI contains two independent audio sub-blocks. Each sub-block has 6its own clock generator and I/O lines controller. 7 8Required properties: 9 - compatible: Should be "st,stm32f4-sai" or "st,stm32h7-sai" 10 - reg: Base address and size of SAI common register set. 11 - clocks: Must contain phandle and clock specifier pairs for each entry 12 in clock-names. 13 - clock-names: Must contain "pclk" "x8k" and "x11k" 14 "pclk": Clock which feeds the peripheral bus interface. 15 Mandatory for "st,stm32h7-sai" compatible. 16 Not used for "st,stm32f4-sai" compatible. 17 "x8k": SAI parent clock for sampling rates multiple of 8kHz. 18 "x11k": SAI parent clock for sampling rates multiple of 11.025kHz. 19 - interrupts: cpu DAI interrupt line shared by SAI sub-blocks 20 21Optional properties: 22 - resets: Reference to a reset controller asserting the SAI 23 24SAI subnodes: 25Two subnodes corresponding to SAI sub-block instances A et B can be defined. 26Subnode can be omitted for unsused sub-block. 27 28SAI subnodes required properties: 29 - compatible: Should be "st,stm32-sai-sub-a" or "st,stm32-sai-sub-b" 30 for SAI sub-block A or B respectively. 31 - reg: Base address and size of SAI sub-block register set. 32 - clocks: Must contain one phandle and clock specifier pair 33 for sai_ck which feeds the internal clock generator. 34 If the SAI shares a master clock, with another SAI set as MCLK 35 clock provider, SAI provider phandle must be specified here. 36 - clock-names: Must contain "sai_ck". 37 Must also contain "MCLK", if SAI shares a master clock, 38 with a SAI set as MCLK clock provider. 39 - dmas: see Documentation/devicetree/bindings/dma/st,stm32-dma.yaml 40 - dma-names: identifier string for each DMA request line 41 "tx": if sai sub-block is configured as playback DAI 42 "rx": if sai sub-block is configured as capture DAI 43 - pinctrl-names: should contain only value "default" 44 - pinctrl-0: see Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml 45 46SAI subnodes Optional properties: 47 - st,sync: specify synchronization mode. 48 By default SAI sub-block is in asynchronous mode. 49 This property sets SAI sub-block as slave of another SAI sub-block. 50 Must contain the phandle and index of the sai sub-block providing 51 the synchronization. 52 - st,iec60958: support S/PDIF IEC6958 protocol for playback 53 IEC60958 protocol is not available for capture. 54 By default, custom protocol is assumed, meaning that protocol is 55 configured according to protocol defined in related DAI link node, 56 such as i2s, left justified, right justified, dsp and pdm protocols. 57 Note: ac97 protocol is not supported by SAI driver 58 - #clock-cells: should be 0. This property must be present if the SAI device 59 is a master clock provider, according to clocks bindings, described in 60 Documentation/devicetree/bindings/clock/clock-bindings.txt. 61 62The device node should contain one 'port' child node with one child 'endpoint' 63node, according to the bindings defined in Documentation/devicetree/bindings/ 64graph.txt. 65 66Example: 67sound_card { 68 compatible = "audio-graph-card"; 69 dais = <&sai1b_port>; 70}; 71 72sai1: sai1@40015800 { 73 compatible = "st,stm32h7-sai"; 74 #address-cells = <1>; 75 #size-cells = <1>; 76 ranges = <0 0x40015800 0x400>; 77 reg = <0x40015800 0x4>; 78 clocks = <&rcc SAI1_CK>, <&rcc PLL1_Q>, <&rcc PLL2_P>; 79 clock-names = "pclk", "x8k", "x11k"; 80 interrupts = <87>; 81 82 sai1a: audio-controller@40015804 { 83 compatible = "st,stm32-sai-sub-a"; 84 reg = <0x4 0x1C>; 85 clocks = <&rcc SAI1_CK>; 86 clock-names = "sai_ck"; 87 dmas = <&dmamux1 1 87 0x400 0x0>; 88 dma-names = "tx"; 89 pinctrl-names = "default"; 90 pinctrl-0 = <&pinctrl_sai1a>; 91 92 sai1b_port: port { 93 cpu_endpoint: endpoint { 94 remote-endpoint = <&codec_endpoint>; 95 format = "i2s"; 96 }; 97 }; 98 }; 99}; 100 101audio-codec { 102 codec_port: port { 103 codec_endpoint: endpoint { 104 remote-endpoint = <&cpu_endpoint>; 105 }; 106 }; 107}; 108