xref: /freebsd/sys/contrib/device-tree/Bindings/sound/nvidia,tegra210-ahub.yaml (revision cfd6422a5217410fbd66f7a7a8a64d9d85e61229) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/sound/nvidia,tegra210-ahub.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Tegra210 AHUB Device Tree Bindings
8
9description: |
10  The Audio Hub (AHUB) comprises a collection of hardware accelerators
11  for audio pre-processing, post-processing and a programmable full
12  crossbar for routing audio data across these accelerators. It has
13  external interfaces such as I2S, DMIC, DSPK. It interfaces with ADMA
14  engine through ADMAIF.
15
16maintainers:
17  - Jon Hunter <jonathanh@nvidia.com>
18  - Sameer Pujar <spujar@nvidia.com>
19
20properties:
21  $nodename:
22    pattern: "^ahub@[0-9a-f]*$"
23
24  compatible:
25    oneOf:
26      - enum:
27          - nvidia,tegra210-ahub
28          - nvidia,tegra186-ahub
29      - items:
30          - const: nvidia,tegra194-ahub
31          - const: nvidia,tegra186-ahub
32
33  reg:
34    maxItems: 1
35
36  clocks:
37    maxItems: 1
38
39  clock-names:
40    const: ahub
41
42  assigned-clocks:
43    maxItems: 1
44
45  assigned-clock-parents:
46    maxItems: 1
47
48  assigned-clock-rates:
49    maxItems: 1
50
51  "#address-cells":
52    const: 1
53
54  "#size-cells":
55    const: 1
56
57  ranges: true
58
59required:
60  - compatible
61  - reg
62  - clocks
63  - clock-names
64  - assigned-clocks
65  - assigned-clock-parents
66  - "#address-cells"
67  - "#size-cells"
68  - ranges
69
70examples:
71  - |
72    #include<dt-bindings/clock/tegra210-car.h>
73
74    ahub@702d0800 {
75        compatible = "nvidia,tegra210-ahub";
76        reg = <0x702d0800 0x800>;
77        clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
78        clock-names = "ahub";
79        assigned-clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
80        assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
81        #address-cells = <1>;
82        #size-cells = <1>;
83        ranges = <0x702d0000 0x702d0000 0x0000e400>;
84
85        // All AHUB child nodes below
86        admaif@702d0000 {
87            compatible = "nvidia,tegra210-admaif";
88            reg = <0x702d0000 0x800>;
89            dmas = <&adma 1>,  <&adma 1>,
90               <&adma 2>,  <&adma 2>,
91               <&adma 3>,  <&adma 3>,
92               <&adma 4>,  <&adma 4>,
93               <&adma 5>,  <&adma 5>,
94               <&adma 6>,  <&adma 6>,
95               <&adma 7>,  <&adma 7>,
96               <&adma 8>,  <&adma 8>,
97               <&adma 9>,  <&adma 9>,
98               <&adma 10>, <&adma 10>;
99            dma-names = "rx1",  "tx1",
100                    "rx2",  "tx2",
101                    "rx3",  "tx3",
102                    "rx4",  "tx4",
103                    "rx5",  "tx5",
104                    "rx6",  "tx6",
105                    "rx7",  "tx7",
106                    "rx8",  "tx8",
107                    "rx9",  "tx9",
108                    "rx10", "tx10";
109        };
110
111        i2s@702d1000 {
112            compatible = "nvidia,tegra210-i2s";
113            reg = <0x702d1000 0x100>;
114            clocks = <&tegra_car TEGRA210_CLK_I2S0>;
115            clock-names = "i2s";
116            assigned-clocks = <&tegra_car TEGRA210_CLK_I2S0>;
117            assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
118            assigned-clock-rates = <1536000>;
119            sound-name-prefix = "I2S1";
120        };
121
122        dmic@702d4000 {
123            compatible = "nvidia,tegra210-dmic";
124            reg = <0x702d4000 0x100>;
125            clocks = <&tegra_car TEGRA210_CLK_DMIC1>;
126            clock-names = "dmic";
127            assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC1>;
128            assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
129            assigned-clock-rates = <3072000>;
130            sound-name-prefix = "DMIC1";
131        };
132
133        // More child nodes to follow
134    };
135
136...
137