xref: /freebsd/sys/contrib/device-tree/Bindings/sound/fsl,spdif.yaml (revision 924226fba12cc9a228c73b956e1b7fa24c60b055) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/sound/fsl,spdif.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Freescale Sony/Philips Digital Interface Format (S/PDIF) Controller
8
9maintainers:
10  - Shengjiu Wang <shengjiu.wang@nxp.com>
11
12description: |
13  The Freescale S/PDIF audio block is a stereo transceiver that allows the
14  processor to receive and transmit digital audio via an coaxial cable or
15  a fibre cable.
16
17properties:
18  compatible:
19    enum:
20      - fsl,imx35-spdif
21      - fsl,vf610-spdif
22      - fsl,imx6sx-spdif
23      - fsl,imx8qm-spdif
24      - fsl,imx8qxp-spdif
25      - fsl,imx8mq-spdif
26      - fsl,imx8mm-spdif
27      - fsl,imx8mn-spdif
28
29  reg:
30    maxItems: 1
31
32  interrupts:
33    maxItems: 1
34
35  dmas:
36    items:
37      - description: DMA controller phandle and request line for RX
38      - description: DMA controller phandle and request line for TX
39
40  dma-names:
41    items:
42      - const: rx
43      - const: tx
44
45  clocks:
46    items:
47      - description: The core clock of spdif controller.
48      - description: Clock for tx0 and rx0.
49      - description: Clock for tx1 and rx1.
50      - description: Clock for tx2 and rx2.
51      - description: Clock for tx3 and rx3.
52      - description: Clock for tx4 and rx4.
53      - description: Clock for tx5 and rx5.
54      - description: Clock for tx6 and rx6.
55      - description: Clock for tx7 and rx7.
56      - description: The spba clock is required when SPDIF is placed as a bus
57          slave of the Shared Peripheral Bus and when two or more bus masters
58          (CPU, DMA or DSP) try to access it. This property is optional depending
59          on the SoC design.
60    minItems: 9
61
62  clock-names:
63    items:
64      - const: core
65      - const: rxtx0
66      - const: rxtx1
67      - const: rxtx2
68      - const: rxtx3
69      - const: rxtx4
70      - const: rxtx5
71      - const: rxtx6
72      - const: rxtx7
73      - const: spba
74    minItems: 9
75
76  big-endian:
77    $ref: /schemas/types.yaml#/definitions/flag
78    description: |
79      If this property is absent, the native endian mode will be in use
80      as default, or the big endian mode will be in use for all the device
81      registers. Set this flag for HCDs with big endian descriptors and big
82      endian registers.
83
84required:
85  - compatible
86  - reg
87  - interrupts
88  - dmas
89  - dma-names
90  - clocks
91  - clock-names
92
93additionalProperties: false
94
95examples:
96  - |
97    spdif@2004000 {
98        compatible = "fsl,imx35-spdif";
99        reg = <0x02004000 0x4000>;
100        interrupts = <0 52 0x04>;
101        dmas = <&sdma 14 18 0>,
102               <&sdma 15 18 0>;
103        dma-names = "rx", "tx";
104        clocks = <&clks 197>, <&clks 3>,
105                 <&clks 197>, <&clks 107>,
106                 <&clks 0>, <&clks 118>,
107                 <&clks 62>, <&clks 139>,
108                 <&clks 0>;
109        clock-names = "core", "rxtx0",
110                      "rxtx1", "rxtx2",
111                      "rxtx3", "rxtx4",
112                      "rxtx5", "rxtx6",
113                      "rxtx7";
114        big-endian;
115    };
116