xref: /freebsd/sys/contrib/device-tree/Bindings/sound/fsl,spdif.yaml (revision 5956d97f4b3204318ceb6aa9c77bd0bc6ea87a41) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/sound/fsl,spdif.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Freescale Sony/Philips Digital Interface Format (S/PDIF) Controller
8
9maintainers:
10  - Shengjiu Wang <shengjiu.wang@nxp.com>
11
12description: |
13  The Freescale S/PDIF audio block is a stereo transceiver that allows the
14  processor to receive and transmit digital audio via an coaxial cable or
15  a fibre cable.
16
17properties:
18  compatible:
19    enum:
20      - fsl,imx35-spdif
21      - fsl,vf610-spdif
22      - fsl,imx6sx-spdif
23      - fsl,imx8qm-spdif
24      - fsl,imx8qxp-spdif
25      - fsl,imx8mq-spdif
26      - fsl,imx8mm-spdif
27      - fsl,imx8mn-spdif
28      - fsl,imx8ulp-spdif
29
30  reg:
31    maxItems: 1
32
33  interrupts:
34    maxItems: 1
35
36  dmas:
37    items:
38      - description: DMA controller phandle and request line for RX
39      - description: DMA controller phandle and request line for TX
40
41  dma-names:
42    items:
43      - const: rx
44      - const: tx
45
46  clocks:
47    items:
48      - description: The core clock of spdif controller.
49      - description: Clock for tx0 and rx0.
50      - description: Clock for tx1 and rx1.
51      - description: Clock for tx2 and rx2.
52      - description: Clock for tx3 and rx3.
53      - description: Clock for tx4 and rx4.
54      - description: Clock for tx5 and rx5.
55      - description: Clock for tx6 and rx6.
56      - description: Clock for tx7 and rx7.
57      - description: The spba clock is required when SPDIF is placed as a bus
58          slave of the Shared Peripheral Bus and when two or more bus masters
59          (CPU, DMA or DSP) try to access it. This property is optional depending
60          on the SoC design.
61    minItems: 9
62
63  clock-names:
64    items:
65      - const: core
66      - const: rxtx0
67      - const: rxtx1
68      - const: rxtx2
69      - const: rxtx3
70      - const: rxtx4
71      - const: rxtx5
72      - const: rxtx6
73      - const: rxtx7
74      - const: spba
75    minItems: 9
76
77  big-endian:
78    $ref: /schemas/types.yaml#/definitions/flag
79    description: |
80      If this property is absent, the native endian mode will be in use
81      as default, or the big endian mode will be in use for all the device
82      registers. Set this flag for HCDs with big endian descriptors and big
83      endian registers.
84
85required:
86  - compatible
87  - reg
88  - interrupts
89  - dmas
90  - dma-names
91  - clocks
92  - clock-names
93
94additionalProperties: false
95
96examples:
97  - |
98    spdif@2004000 {
99        compatible = "fsl,imx35-spdif";
100        reg = <0x02004000 0x4000>;
101        interrupts = <0 52 0x04>;
102        dmas = <&sdma 14 18 0>,
103               <&sdma 15 18 0>;
104        dma-names = "rx", "tx";
105        clocks = <&clks 197>, <&clks 3>,
106                 <&clks 197>, <&clks 107>,
107                 <&clks 0>, <&clks 118>,
108                 <&clks 62>, <&clks 139>,
109                 <&clks 0>;
110        clock-names = "core", "rxtx0",
111                      "rxtx1", "rxtx2",
112                      "rxtx3", "rxtx4",
113                      "rxtx5", "rxtx6",
114                      "rxtx7";
115        big-endian;
116    };
117