1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/sound/fsl,sai.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Freescale Synchronous Audio Interface (SAI). 8 9maintainers: 10 - Shengjiu Wang <shengjiu.wang@nxp.com> 11 12description: | 13 The SAI is based on I2S module that used communicating with audio codecs, 14 which provides a synchronous audio interface that supports fullduplex 15 serial interfaces with frame synchronization such as I2S, AC97, TDM, and 16 codec/DSP interfaces. 17 18properties: 19 compatible: 20 oneOf: 21 - items: 22 - enum: 23 - fsl,imx6ul-sai 24 - fsl,imx7d-sai 25 - const: fsl,imx6sx-sai 26 27 - items: 28 - enum: 29 - fsl,imx8mm-sai 30 - fsl,imx8mn-sai 31 - fsl,imx8mp-sai 32 - const: fsl,imx8mq-sai 33 34 - items: 35 - enum: 36 - fsl,imx6sx-sai 37 - fsl,imx7ulp-sai 38 - fsl,imx8mq-sai 39 - fsl,imx8qm-sai 40 - fsl,imx8ulp-sai 41 - fsl,imx93-sai 42 - fsl,vf610-sai 43 44 reg: 45 maxItems: 1 46 47 clocks: 48 items: 49 - description: The ipg clock for register access 50 - description: master clock source 0 (obsoleted) 51 - description: master clock source 1 52 - description: master clock source 2 53 - description: master clock source 3 54 - description: PLL clock source for 8kHz series 55 - description: PLL clock source for 11kHz series 56 minItems: 4 57 58 clock-names: 59 oneOf: 60 - items: 61 - const: bus 62 - const: mclk0 63 - const: mclk1 64 - const: mclk2 65 - const: mclk3 66 - const: pll8k 67 - const: pll11k 68 minItems: 5 69 - items: 70 - const: bus 71 - const: mclk1 72 - const: mclk2 73 - const: mclk3 74 - const: pll8k 75 - const: pll11k 76 minItems: 4 77 78 dmas: 79 maxItems: 2 80 81 dma-names: 82 maxItems: 2 83 84 interrupts: 85 items: 86 - description: receive and transmit interrupt 87 88 big-endian: 89 description: | 90 required if all the SAI registers are big-endian rather than little-endian. 91 type: boolean 92 93 fsl,dataline: 94 $ref: /schemas/types.yaml#/definitions/uint32-matrix 95 description: | 96 Configure the dataline. It has 3 value for each configuration 97 maxItems: 16 98 items: 99 items: 100 - description: format Default(0), I2S(1) or PDM(2) 101 enum: [0, 1, 2] 102 - description: dataline mask for 'rx' 103 - description: dataline mask for 'tx' 104 105 fsl,sai-mclk-direction-output: 106 description: SAI will output the SAI MCLK clock. 107 type: boolean 108 109 fsl,sai-synchronous-rx: 110 description: | 111 SAI will work in the synchronous mode (sync Tx with Rx) which means 112 both the transmitter and the receiver will send and receive data by 113 following receiver's bit clocks and frame sync clocks. 114 type: boolean 115 116 fsl,sai-asynchronous: 117 description: | 118 SAI will work in the asynchronous mode, which means both transmitter 119 and receiver will send and receive data by following their own bit clocks 120 and frame sync clocks separately. 121 If both fsl,sai-asynchronous and fsl,sai-synchronous-rx are absent, the 122 default synchronous mode (sync Rx with Tx) will be used, which means both 123 transmitter and receiver will send and receive data by following clocks 124 of transmitter. 125 type: boolean 126 127 fsl,shared-interrupt: 128 description: Interrupt is shared with other modules. 129 type: boolean 130 131 lsb-first: 132 description: | 133 Configures whether the LSB or the MSB is transmitted 134 first for the fifo data. If this property is absent, 135 the MSB is transmitted first as default, or the LSB 136 is transmitted first. 137 type: boolean 138 139 "#sound-dai-cells": 140 const: 0 141 description: optional, some dts node didn't add it. 142 143allOf: 144 - $ref: dai-common.yaml# 145 - if: 146 properties: 147 compatible: 148 contains: 149 const: fsl,vf610-sai 150 then: 151 properties: 152 dmas: 153 items: 154 - description: DMA controller phandle and request line for TX 155 - description: DMA controller phandle and request line for RX 156 dma-names: 157 items: 158 - const: tx 159 - const: rx 160 else: 161 properties: 162 dmas: 163 items: 164 - description: DMA controller phandle and request line for RX 165 - description: DMA controller phandle and request line for TX 166 dma-names: 167 items: 168 - const: rx 169 - const: tx 170 - if: 171 required: 172 - fsl,sai-asynchronous 173 then: 174 properties: 175 fsl,sai-synchronous-rx: false 176 177required: 178 - compatible 179 - reg 180 - clocks 181 - clock-names 182 - dmas 183 - dma-names 184 - interrupts 185 186unevaluatedProperties: false 187 188examples: 189 - | 190 #include <dt-bindings/interrupt-controller/arm-gic.h> 191 #include <dt-bindings/clock/vf610-clock.h> 192 sai2: sai@40031000 { 193 compatible = "fsl,vf610-sai"; 194 reg = <0x40031000 0x1000>; 195 interrupts = <86 IRQ_TYPE_LEVEL_HIGH>; 196 pinctrl-names = "default"; 197 pinctrl-0 = <&pinctrl_sai2_1>; 198 clocks = <&clks VF610_CLK_PLATFORM_BUS>, 199 <&clks VF610_CLK_SAI2>, 200 <&clks 0>, <&clks 0>; 201 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 202 dma-names = "tx", "rx"; 203 dmas = <&edma0 0 21>, 204 <&edma0 0 20>; 205 big-endian; 206 lsb-first; 207 }; 208 209 - | 210 #include <dt-bindings/interrupt-controller/arm-gic.h> 211 #include <dt-bindings/clock/imx8mm-clock.h> 212 sai1: sai@30010000 { 213 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; 214 reg = <0x30010000 0x10000>; 215 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 216 clocks = <&clk IMX8MM_CLK_SAI1_IPG>, 217 <&clk IMX8MM_CLK_DUMMY>, 218 <&clk IMX8MM_CLK_SAI1_ROOT>, 219 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; 220 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 221 dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>; 222 dma-names = "rx", "tx"; 223 fsl,dataline = <1 0xff 0xff 2 0xff 0x11>; 224 #sound-dai-cells = <0>; 225 }; 226