1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/soc/ti/wkup-m3-ipc.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Wakeup M3 IPC device 8 9maintainers: 10 - Dave Gerlach <d-gerlach@ti.com> 11 - Drew Fustini <dfustini@baylibre.com> 12 13description: |+ 14 The TI AM33xx and AM43xx family of devices use a small Cortex M3 co-processor 15 (commonly referred to as Wakeup M3 or CM3) to help with various low power tasks 16 that cannot be controlled from the MPU, like suspend/resume and certain deep 17 C-states for CPU Idle. Once the wkup_m3_ipc driver uses the wkup_m3_rproc driver 18 to boot the wkup_m3, it handles communication with the CM3 using IPC registers 19 present in the SoC's control module and a mailbox. The wkup_m3_ipc exposes an 20 API to allow the SoC PM code to execute specific PM tasks. 21 22 Wkup M3 Device Node 23 ==================== 24 A wkup_m3_ipc device node is used to represent the IPC registers within an 25 SoC. 26 27 Support for VTT Toggle with GPIO pin 28 ==================================== 29 On some boards like the AM335x EVM-SK and the AM437x GP EVM, a GPIO pin is 30 connected to the enable pin on the DDR VTT regulator. This allows the 31 regulator to be disabled upon suspend and enabled upon resume. Please note 32 that the GPIO pin must be part of the GPIO0 module as only this GPIO module 33 is in the wakeup power domain. 34 35 Support for IO Isolation 36 ======================== 37 On AM437x SoCs, certain pins can be forced into an alternate state when IO 38 isolation is activated. Those pins have pad control registers prefixed by 39 'CTRL_CONF_' that contain DS0 (e.g. deep sleep) configuration bits that can 40 override the pin's existing bias (pull-up/pull-down) and value (high/low) when 41 IO isolation is active. 42 43 Support for I2C PMIC Voltage Scaling 44 ==================================== 45 It is possible to pass the name of a binary file to load into the CM3 memory. 46 The binary data is the I2C sequences for the CM3 to send out to the PMIC 47 during low power mode entry. 48 49properties: 50 compatible: 51 enum: 52 - ti,am3352-wkup-m3-ipc # for AM33xx SoCs 53 - ti,am4372-wkup-m3-ipc # for AM43xx SoCs 54 55 reg: 56 description: 57 The IPC register address space to communicate with the Wakeup M3 processor 58 maxItems: 1 59 60 interrupts: 61 description: wkup_m3 interrupt that signals the MPU 62 maxItems: 1 63 64 ti,rproc: 65 $ref: /schemas/types.yaml#/definitions/phandle 66 description: 67 phandle to the wkup_m3 rproc node so the IPC driver can boot it 68 69 mboxes: 70 description: 71 phandles used by IPC framework to get correct mbox 72 channel for communication. Must point to appropriate 73 mbox_wkupm3 child node. 74 maxItems: 1 75 76 firmware-name: 77 description: 78 Name of binary file with I2C sequences for PMIC voltage scaling 79 80 ti,vtt-gpio-pin: 81 $ref: /schemas/types.yaml#/definitions/uint32 82 description: GPIO pin connected to enable pin on VTT regulator 83 84 ti,set-io-isolation: 85 type: boolean 86 description: 87 If this property is present, then the wkup_m3_ipc driver will instruct 88 the CM3 firmware to activate IO isolation when suspending to deep sleep. 89 This can be leveraged by a board design to put other devices on the board 90 into a low power state. 91 92allOf: 93 - if: 94 properties: 95 compatible: 96 not: 97 contains: 98 const: ti,am4372-wkup-m3-ipc 99 then: 100 properties: 101 ti,set-io-isolation: false 102 103required: 104 - compatible 105 - reg 106 - interrupts 107 - ti,rproc 108 - mboxes 109 110additionalProperties: false 111 112examples: 113 - | 114 /* Example for AM335x SoC */ 115 soc { 116 #address-cells = <1>; 117 #size-cells = <1>; 118 119 am335x_mailbox: mailbox { 120 #mbox-cells = <1>; 121 }; 122 123 wkup_m3_ipc@1324 { 124 compatible = "ti,am3352-wkup-m3-ipc"; 125 reg = <0x1324 0x24>; 126 interrupts = <78>; 127 ti,rproc = <&wkup_m3>; 128 mboxes = <&am335x_mailbox &mbox_wkupm3>; 129 ti,vtt-gpio-pin = <7>; 130 firmware-name = "am335x-evm-scale-data.bin"; 131 }; 132 }; 133 134 - | 135 /* 136 * Example for AM473x SoC: 137 * On the AM437x-GP-EVM board, gpio5_7 is wired to enable pin of the DDR VTT 138 * regulator. The 'ddr_vtt_toggle_default' pinmux node configures gpio5_7 139 * for pull-up during normal system operation. However, the DS0 (deep sleep) 140 * state of the pin is configured for pull-down and thus the VTT regulator 141 * will be disabled to save power when IO isolation is active. Note that 142 * this method is an alternative to using the 'ti,vtt-gpio-pin' property. 143 */ 144 #include <dt-bindings/pinctrl/am43xx.h> 145 soc { 146 #address-cells = <1>; 147 #size-cells = <1>; 148 149 am437x_mailbox: mailbox { 150 #mbox-cells = <1>; 151 }; 152 153 am43xx_pinmux { 154 pinctrl-names = "default"; 155 pinctrl-0 = <&ddr3_vtt_toggle_default>; 156 157 ddr3_vtt_toggle_default: ddr_vtt_toggle_default { 158 pinctrl-single,pins = < 159 0x25C (DS0_PULL_UP_DOWN_EN | PIN_OUTPUT_PULLUP | DS0_FORCE_OFF_MODE | MUX_MODE7) 160 >; 161 }; 162 }; 163 164 wkup_m3_ipc@1324 { 165 compatible = "ti,am4372-wkup-m3-ipc"; 166 reg = <0x1324 0x24>; 167 interrupts = <78>; 168 ti,rproc = <&wkup_m3>; 169 mboxes = <&am437x_mailbox &mbox_wkupm3>; 170 ti,set-io-isolation; 171 firmware-name = "am43x-evm-scale-data.bin"; 172 }; 173 }; 174 175... 176