1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/soc/ti/ti,pruss.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: |+ 8 TI Programmable Real-Time Unit and Industrial Communication Subsystem 9 10maintainers: 11 - Suman Anna <s-anna@ti.com> 12 13description: |+ 14 15 The Programmable Real-Time Unit and Industrial Communication Subsystem 16 (PRU-ICSS a.k.a. PRUSS) is present on various TI SoCs such as AM335x, AM437x, 17 Keystone 66AK2G, OMAP-L138/DA850 etc. A PRUSS consists of dual 32-bit RISC 18 cores (Programmable Real-Time Units, or PRUs), shared RAM, data and 19 instruction RAMs, some internal peripheral modules to facilitate industrial 20 communication, and an interrupt controller. 21 22 The programmable nature of the PRUs provide flexibility to implement custom 23 peripheral interfaces, fast real-time responses, or specialized data handling. 24 The common peripheral modules include the following, 25 - an Ethernet MII_RT module with two MII ports 26 - an MDIO port to control external Ethernet PHYs 27 - an Industrial Ethernet Peripheral (IEP) to manage/generate Industrial 28 Ethernet functions 29 - an Enhanced Capture Module (eCAP) 30 - an Industrial Ethernet Timer with 7/9 capture and 16 compare events 31 - a 16550-compatible UART to support PROFIBUS 32 - Enhanced GPIO with async capture and serial support 33 34 A PRU-ICSS subsystem can have up to three shared data memories. A PRU core 35 acts on a primary Data RAM (there are usually 2 Data RAMs) at its address 36 0x0, but also has access to a secondary Data RAM (primary to the other PRU 37 core) at its address 0x2000. A shared Data RAM, if present, can be accessed 38 by both the PRU cores. The Interrupt Controller (INTC) and a CFG module are 39 common to both the PRU cores. Each PRU core also has a private instruction 40 RAM, and specific register spaces for Control and Debug functionalities. 41 42 Various sub-modules within a PRU-ICSS subsystem are represented as individual 43 nodes and are defined using a parent-child hierarchy depending on their 44 integration within the IP and the SoC. These nodes are described in the 45 following sections. 46 47 48 PRU-ICSS Node 49 ============== 50 Each PRU-ICSS instance is represented as its own node with the individual PRU 51 processor cores, the memories node, an INTC node and an MDIO node represented 52 as child nodes within this PRUSS node. This node shall be a child of the 53 corresponding interconnect bus nodes or target-module nodes. 54 55 See ../../mfd/syscon.yaml for generic SysCon binding details. 56 57 58properties: 59 $nodename: 60 pattern: "^(pruss|icssg)@[0-9a-f]+$" 61 62 compatible: 63 enum: 64 - ti,am3356-pruss # for AM335x SoC family 65 - ti,am4376-pruss0 # for AM437x SoC family and PRUSS unit 0 66 - ti,am4376-pruss1 # for AM437x SoC family and PRUSS unit 1 67 - ti,am5728-pruss # for AM57xx SoC family 68 - ti,am625-pruss # for K3 AM62x SoC family 69 - ti,am642-icssg # for K3 AM64x SoC family 70 - ti,am654-icssg # for K3 AM65x SoC family 71 - ti,j721e-icssg # for K3 J721E SoC family 72 - ti,k2g-pruss # for 66AK2G SoC family 73 74 reg: 75 maxItems: 1 76 77 "#address-cells": 78 const: 1 79 80 "#size-cells": 81 const: 1 82 83 ranges: 84 maxItems: 1 85 86 dma-ranges: 87 maxItems: 1 88 89 dma-coherent: true 90 91 power-domains: 92 description: | 93 This property is as per sci-pm-domain.txt. 94 95patternProperties: 96 97 memories@[a-f0-9]+$: 98 description: | 99 The various Data RAMs within a single PRU-ICSS unit are represented as a 100 single node with the name 'memories'. 101 102 type: object 103 104 properties: 105 reg: 106 minItems: 2 # On AM437x one of two PRUSS units don't contain Shared RAM. 107 items: 108 - description: Address and size of the Data RAM0. 109 - description: Address and size of the Data RAM1. 110 - description: | 111 Address and size of the Shared Data RAM. Note that on AM437x one 112 of two PRUSS units don't contain Shared RAM, while the second one 113 has it. 114 115 reg-names: 116 minItems: 2 117 items: 118 - const: dram0 119 - const: dram1 120 - const: shrdram2 121 122 required: 123 - reg 124 - reg-names 125 126 additionalProperties: false 127 128 cfg@[a-f0-9]+$: 129 description: | 130 PRU-ICSS configuration space. CFG sub-module represented as a SysCon. 131 132 type: object 133 134 properties: 135 compatible: 136 items: 137 - const: ti,pruss-cfg 138 - const: syscon 139 140 "#address-cells": 141 const: 1 142 143 "#size-cells": 144 const: 1 145 146 reg: 147 maxItems: 1 148 149 ranges: 150 maxItems: 1 151 152 clocks: 153 type: object 154 155 properties: 156 "#address-cells": 157 const: 1 158 159 "#size-cells": 160 const: 0 161 162 patternProperties: 163 coreclk-mux@[a-f0-9]+$: 164 description: | 165 This is applicable only for ICSSG (K3 SoCs). The ICSSG modules 166 core clock can be set to one of the 2 sources: ICSSG_CORE_CLK or 167 ICSSG_ICLK. This node models this clock mux and should have the 168 name "coreclk-mux". 169 170 type: object 171 172 properties: 173 '#clock-cells': 174 const: 0 175 176 clocks: 177 items: 178 - description: ICSSG_CORE Clock 179 - description: ICSSG_ICLK Clock 180 181 assigned-clocks: 182 maxItems: 1 183 184 assigned-clock-parents: 185 maxItems: 1 186 description: | 187 Standard assigned-clocks-parents definition used for selecting 188 mux parent (one of the mux input). 189 190 reg: 191 maxItems: 1 192 193 required: 194 - clocks 195 196 additionalProperties: false 197 198 iepclk-mux@[a-f0-9]+$: 199 description: | 200 The IEP module can get its clock from 2 sources: ICSSG_IEP_CLK or 201 CORE_CLK (OCP_CLK in older SoCs). This node models this clock 202 mux and should have the name "iepclk-mux". 203 204 type: object 205 206 properties: 207 '#clock-cells': 208 const: 0 209 210 clocks: 211 items: 212 - description: ICSSG_IEP Clock 213 - description: Core Clock (OCP Clock in older SoCs) 214 215 assigned-clocks: 216 maxItems: 1 217 218 assigned-clock-parents: 219 maxItems: 1 220 description: | 221 Standard assigned-clocks-parents definition used for selecting 222 mux parent (one of the mux input). 223 224 reg: 225 maxItems: 1 226 227 required: 228 - clocks 229 230 additionalProperties: false 231 232 additionalProperties: false 233 234 iep@[a-f0-9]+$: 235 description: | 236 Industrial Ethernet Peripheral to manage/generate Industrial Ethernet 237 functions such as time stamping. Each PRUSS has either 1 IEP (on AM335x, 238 AM437x, AM57xx & 66AK2G SoCs) or 2 IEPs (on K3 AM65x, J721E & AM64x SoCs). 239 IEP is used for creating PTP clocks and generating PPS signals. 240 241 type: object 242 243 mii-rt@[a-f0-9]+$: 244 description: | 245 Real-Time Ethernet to support multiple industrial communication protocols. 246 MII-RT sub-module represented as a SysCon. 247 248 type: object 249 250 properties: 251 compatible: 252 items: 253 - const: ti,pruss-mii 254 - const: syscon 255 256 reg: 257 maxItems: 1 258 259 additionalProperties: false 260 261 mii-g-rt@[a-f0-9]+$: 262 description: | 263 The Real-time Media Independent Interface to support multiple industrial 264 communication protocols (G stands for Gigabit). MII-G-RT sub-module 265 represented as a SysCon. 266 267 type: object 268 269 properties: 270 compatible: 271 items: 272 - const: ti,pruss-mii-g 273 - const: syscon 274 275 reg: 276 maxItems: 1 277 278 additionalProperties: false 279 280 interrupt-controller@[a-f0-9]+$: 281 description: | 282 PRUSS INTC Node. Each PRUSS has a single interrupt controller instance 283 that is common to all the PRU cores. This should be represented as an 284 interrupt-controller node. 285 $ref: /schemas/interrupt-controller/ti,pruss-intc.yaml# 286 type: object 287 288 mdio@[a-f0-9]+$: 289 description: | 290 MDIO Node. Each PRUSS has an MDIO module that can be used to control 291 external PHYs. The MDIO module used within the PRU-ICSS is an instance of 292 the MDIO Controller used in TI Davinci SoCs. 293 $ref: /schemas/net/ti,davinci-mdio.yaml# 294 type: object 295 296 "^(pru|rtu|txpru)@[0-9a-f]+$": 297 description: | 298 PRU Node. Each PRUSS has dual PRU cores, each represented as a RemoteProc 299 device through a PRU child node each. Each node can optionally be rendered 300 inactive by using the standard DT string property, "status". The ICSSG IP 301 present on K3 SoCs have additional auxiliary PRU cores with slightly 302 different IP integration. 303 $ref: /schemas/remoteproc/ti,pru-rproc.yaml# 304 type: object 305 306required: 307 - compatible 308 - reg 309 - ranges 310 311additionalProperties: false 312 313# Due to inability of correctly verifying sub-nodes with an @address through 314# the "required" list, the required sub-nodes below are commented out for now. 315 316#required: 317# - memories 318# - interrupt-controller 319# - pru 320 321allOf: 322 - if: 323 properties: 324 compatible: 325 contains: 326 enum: 327 - ti,k2g-pruss 328 - ti,am654-icssg 329 - ti,j721e-icssg 330 - ti,am642-icssg 331 then: 332 required: 333 - power-domains 334 335 - if: 336 properties: 337 compatible: 338 contains: 339 enum: 340 - ti,k2g-pruss 341 then: 342 required: 343 - dma-coherent 344 345examples: 346 - | 347 348 /* Example 1 AM33xx PRU-ICSS */ 349 pruss: pruss@0 { 350 compatible = "ti,am3356-pruss"; 351 reg = <0x0 0x80000>; 352 #address-cells = <1>; 353 #size-cells = <1>; 354 ranges; 355 356 pruss_mem: memories@0 { 357 reg = <0x0 0x2000>, 358 <0x2000 0x2000>, 359 <0x10000 0x3000>; 360 reg-names = "dram0", "dram1", "shrdram2"; 361 }; 362 363 pruss_cfg: cfg@26000 { 364 compatible = "ti,pruss-cfg", "syscon"; 365 #address-cells = <1>; 366 #size-cells = <1>; 367 reg = <0x26000 0x2000>; 368 ranges = <0x00 0x26000 0x2000>; 369 370 clocks { 371 #address-cells = <1>; 372 #size-cells = <0>; 373 374 pruss_iepclk_mux: iepclk-mux@30 { 375 reg = <0x30>; 376 #clock-cells = <0>; 377 clocks = <&l3_gclk>, /* icss_iep */ 378 <&pruss_ocp_gclk>; /* icss_ocp */ 379 }; 380 }; 381 }; 382 383 pruss_mii_rt: mii-rt@32000 { 384 compatible = "ti,pruss-mii", "syscon"; 385 reg = <0x32000 0x58>; 386 }; 387 388 pruss_intc: interrupt-controller@20000 { 389 compatible = "ti,pruss-intc"; 390 reg = <0x20000 0x2000>; 391 interrupt-controller; 392 #interrupt-cells = <3>; 393 interrupts = <20 21 22 23 24 25 26 27>; 394 interrupt-names = "host_intr0", "host_intr1", 395 "host_intr2", "host_intr3", 396 "host_intr4", "host_intr5", 397 "host_intr6", "host_intr7"; 398 }; 399 400 pru0: pru@34000 { 401 compatible = "ti,am3356-pru"; 402 reg = <0x34000 0x2000>, 403 <0x22000 0x400>, 404 <0x22400 0x100>; 405 reg-names = "iram", "control", "debug"; 406 firmware-name = "am335x-pru0-fw"; 407 }; 408 409 pru1: pru@38000 { 410 compatible = "ti,am3356-pru"; 411 reg = <0x38000 0x2000>, 412 <0x24000 0x400>, 413 <0x24400 0x100>; 414 reg-names = "iram", "control", "debug"; 415 firmware-name = "am335x-pru1-fw"; 416 }; 417 418 pruss_mdio: mdio@32400 { 419 compatible = "ti,davinci_mdio"; 420 reg = <0x32400 0x90>; 421 clocks = <&dpll_core_m4_ck>; 422 clock-names = "fck"; 423 bus_freq = <1000000>; 424 #address-cells = <1>; 425 #size-cells = <0>; 426 }; 427 }; 428 429 - | 430 431 /* Example 2 AM43xx PRU-ICSS with PRUSS1 node */ 432 #include <dt-bindings/interrupt-controller/arm-gic.h> 433 pruss1: pruss@0 { 434 compatible = "ti,am4376-pruss1"; 435 reg = <0x0 0x40000>; 436 #address-cells = <1>; 437 #size-cells = <1>; 438 ranges; 439 440 pruss1_mem: memories@0 { 441 reg = <0x0 0x2000>, 442 <0x2000 0x2000>, 443 <0x10000 0x8000>; 444 reg-names = "dram0", "dram1", "shrdram2"; 445 }; 446 447 pruss1_cfg: cfg@26000 { 448 compatible = "ti,pruss-cfg", "syscon"; 449 #address-cells = <1>; 450 #size-cells = <1>; 451 reg = <0x26000 0x2000>; 452 ranges = <0x00 0x26000 0x2000>; 453 454 clocks { 455 #address-cells = <1>; 456 #size-cells = <0>; 457 458 pruss1_iepclk_mux: iepclk-mux@30 { 459 reg = <0x30>; 460 #clock-cells = <0>; 461 clocks = <&sysclk_div>, /* icss_iep */ 462 <&pruss_ocp_gclk>; /* icss_ocp */ 463 }; 464 }; 465 }; 466 467 pruss1_mii_rt: mii-rt@32000 { 468 compatible = "ti,pruss-mii", "syscon"; 469 reg = <0x32000 0x58>; 470 }; 471 472 pruss1_intc: interrupt-controller@20000 { 473 compatible = "ti,pruss-intc"; 474 reg = <0x20000 0x2000>; 475 interrupt-controller; 476 #interrupt-cells = <3>; 477 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 478 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 479 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 480 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 481 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 482 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 483 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 484 interrupt-names = "host_intr0", "host_intr1", 485 "host_intr2", "host_intr3", 486 "host_intr4", 487 "host_intr6", "host_intr7"; 488 ti,irqs-reserved = /bits/ 8 <0x20>; /* BIT(5) */ 489 }; 490 491 pru1_0: pru@34000 { 492 compatible = "ti,am4376-pru"; 493 reg = <0x34000 0x3000>, 494 <0x22000 0x400>, 495 <0x22400 0x100>; 496 reg-names = "iram", "control", "debug"; 497 firmware-name = "am437x-pru1_0-fw"; 498 }; 499 500 pru1_1: pru@38000 { 501 compatible = "ti,am4376-pru"; 502 reg = <0x38000 0x3000>, 503 <0x24000 0x400>, 504 <0x24400 0x100>; 505 reg-names = "iram", "control", "debug"; 506 firmware-name = "am437x-pru1_1-fw"; 507 }; 508 509 pruss1_mdio: mdio@32400 { 510 compatible = "ti,davinci_mdio"; 511 reg = <0x32400 0x90>; 512 clocks = <&dpll_core_m4_ck>; 513 clock-names = "fck"; 514 bus_freq = <1000000>; 515 #address-cells = <1>; 516 #size-cells = <0>; 517 }; 518 }; 519 520... 521