1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/soc/ti/ti,pruss.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: |+ 8 TI Programmable Real-Time Unit and Industrial Communication Subsystem 9 10maintainers: 11 - Suman Anna <s-anna@ti.com> 12 13description: |+ 14 15 The Programmable Real-Time Unit and Industrial Communication Subsystem 16 (PRU-ICSS a.k.a. PRUSS) is present on various TI SoCs such as AM335x, AM437x, 17 Keystone 66AK2G, OMAP-L138/DA850 etc. A PRUSS consists of dual 32-bit RISC 18 cores (Programmable Real-Time Units, or PRUs), shared RAM, data and 19 instruction RAMs, some internal peripheral modules to facilitate industrial 20 communication, and an interrupt controller. 21 22 The programmable nature of the PRUs provide flexibility to implement custom 23 peripheral interfaces, fast real-time responses, or specialized data handling. 24 The common peripheral modules include the following, 25 - an Ethernet MII_RT module with two MII ports 26 - an MDIO port to control external Ethernet PHYs 27 - an Industrial Ethernet Peripheral (IEP) to manage/generate Industrial 28 Ethernet functions 29 - an Enhanced Capture Module (eCAP) 30 - an Industrial Ethernet Timer with 7/9 capture and 16 compare events 31 - a 16550-compatible UART to support PROFIBUS 32 - Enhanced GPIO with async capture and serial support 33 34 A PRU-ICSS subsystem can have up to three shared data memories. A PRU core 35 acts on a primary Data RAM (there are usually 2 Data RAMs) at its address 36 0x0, but also has access to a secondary Data RAM (primary to the other PRU 37 core) at its address 0x2000. A shared Data RAM, if present, can be accessed 38 by both the PRU cores. The Interrupt Controller (INTC) and a CFG module are 39 common to both the PRU cores. Each PRU core also has a private instruction 40 RAM, and specific register spaces for Control and Debug functionalities. 41 42 Various sub-modules within a PRU-ICSS subsystem are represented as individual 43 nodes and are defined using a parent-child hierarchy depending on their 44 integration within the IP and the SoC. These nodes are described in the 45 following sections. 46 47 48 PRU-ICSS Node 49 ============== 50 Each PRU-ICSS instance is represented as its own node with the individual PRU 51 processor cores, the memories node, an INTC node and an MDIO node represented 52 as child nodes within this PRUSS node. This node shall be a child of the 53 corresponding interconnect bus nodes or target-module nodes. 54 55 See ../../mfd/syscon.yaml for generic SysCon binding details. 56 57 58properties: 59 $nodename: 60 pattern: "^(pruss|icssg)@[0-9a-f]+$" 61 62 compatible: 63 enum: 64 - ti,am3356-pruss # for AM335x SoC family 65 - ti,am4376-pruss0 # for AM437x SoC family and PRUSS unit 0 66 - ti,am4376-pruss1 # for AM437x SoC family and PRUSS unit 1 67 - ti,am5728-pruss # for AM57xx SoC family 68 - ti,k2g-pruss # for 66AK2G SoC family 69 - ti,am654-icssg # for K3 AM65x SoC family 70 - ti,j721e-icssg # for K3 J721E SoC family 71 - ti,am642-icssg # for K3 AM64x SoC family 72 73 reg: 74 maxItems: 1 75 76 "#address-cells": 77 const: 1 78 79 "#size-cells": 80 const: 1 81 82 ranges: 83 maxItems: 1 84 85 dma-ranges: 86 maxItems: 1 87 88 dma-coherent: true 89 90 power-domains: 91 description: | 92 This property is as per sci-pm-domain.txt. 93 94patternProperties: 95 96 memories@[a-f0-9]+$: 97 description: | 98 The various Data RAMs within a single PRU-ICSS unit are represented as a 99 single node with the name 'memories'. 100 101 type: object 102 103 properties: 104 reg: 105 minItems: 2 # On AM437x one of two PRUSS units don't contain Shared RAM. 106 items: 107 - description: Address and size of the Data RAM0. 108 - description: Address and size of the Data RAM1. 109 - description: | 110 Address and size of the Shared Data RAM. Note that on AM437x one 111 of two PRUSS units don't contain Shared RAM, while the second one 112 has it. 113 114 reg-names: 115 minItems: 2 116 items: 117 - const: dram0 118 - const: dram1 119 - const: shrdram2 120 121 required: 122 - reg 123 - reg-names 124 125 additionalProperties: false 126 127 cfg@[a-f0-9]+$: 128 description: | 129 PRU-ICSS configuration space. CFG sub-module represented as a SysCon. 130 131 type: object 132 133 properties: 134 compatible: 135 items: 136 - const: ti,pruss-cfg 137 - const: syscon 138 139 "#address-cells": 140 const: 1 141 142 "#size-cells": 143 const: 1 144 145 reg: 146 maxItems: 1 147 148 ranges: 149 maxItems: 1 150 151 clocks: 152 type: object 153 154 properties: 155 "#address-cells": 156 const: 1 157 158 "#size-cells": 159 const: 0 160 161 patternProperties: 162 coreclk-mux@[a-f0-9]+$: 163 description: | 164 This is applicable only for ICSSG (K3 SoCs). The ICSSG modules 165 core clock can be set to one of the 2 sources: ICSSG_CORE_CLK or 166 ICSSG_ICLK. This node models this clock mux and should have the 167 name "coreclk-mux". 168 169 type: object 170 171 properties: 172 '#clock-cells': 173 const: 0 174 175 clocks: 176 items: 177 - description: ICSSG_CORE Clock 178 - description: ICSSG_ICLK Clock 179 180 assigned-clocks: 181 maxItems: 1 182 183 assigned-clock-parents: 184 maxItems: 1 185 description: | 186 Standard assigned-clocks-parents definition used for selecting 187 mux parent (one of the mux input). 188 189 reg: 190 maxItems: 1 191 192 required: 193 - clocks 194 195 additionalProperties: false 196 197 iepclk-mux@[a-f0-9]+$: 198 description: | 199 The IEP module can get its clock from 2 sources: ICSSG_IEP_CLK or 200 CORE_CLK (OCP_CLK in older SoCs). This node models this clock 201 mux and should have the name "iepclk-mux". 202 203 type: object 204 205 properties: 206 '#clock-cells': 207 const: 0 208 209 clocks: 210 items: 211 - description: ICSSG_IEP Clock 212 - description: Core Clock (OCP Clock in older SoCs) 213 214 assigned-clocks: 215 maxItems: 1 216 217 assigned-clock-parents: 218 maxItems: 1 219 description: | 220 Standard assigned-clocks-parents definition used for selecting 221 mux parent (one of the mux input). 222 223 reg: 224 maxItems: 1 225 226 required: 227 - clocks 228 229 additionalProperties: false 230 231 additionalProperties: false 232 233 iep@[a-f0-9]+$: 234 description: | 235 Industrial Ethernet Peripheral to manage/generate Industrial Ethernet 236 functions such as time stamping. Each PRUSS has either 1 IEP (on AM335x, 237 AM437x, AM57xx & 66AK2G SoCs) or 2 IEPs (on K3 AM65x, J721E & AM64x SoCs). 238 IEP is used for creating PTP clocks and generating PPS signals. 239 240 type: object 241 242 mii-rt@[a-f0-9]+$: 243 description: | 244 Real-Time Ethernet to support multiple industrial communication protocols. 245 MII-RT sub-module represented as a SysCon. 246 247 type: object 248 249 properties: 250 compatible: 251 items: 252 - const: ti,pruss-mii 253 - const: syscon 254 255 reg: 256 maxItems: 1 257 258 additionalProperties: false 259 260 mii-g-rt@[a-f0-9]+$: 261 description: | 262 The Real-time Media Independent Interface to support multiple industrial 263 communication protocols (G stands for Gigabit). MII-G-RT sub-module 264 represented as a SysCon. 265 266 type: object 267 268 properties: 269 compatible: 270 items: 271 - const: ti,pruss-mii-g 272 - const: syscon 273 274 reg: 275 maxItems: 1 276 277 additionalProperties: false 278 279 interrupt-controller@[a-f0-9]+$: 280 description: | 281 PRUSS INTC Node. Each PRUSS has a single interrupt controller instance 282 that is common to all the PRU cores. This should be represented as an 283 interrupt-controller node. 284 $ref: /schemas/interrupt-controller/ti,pruss-intc.yaml# 285 type: object 286 287 mdio@[a-f0-9]+$: 288 description: | 289 MDIO Node. Each PRUSS has an MDIO module that can be used to control 290 external PHYs. The MDIO module used within the PRU-ICSS is an instance of 291 the MDIO Controller used in TI Davinci SoCs. 292 $ref: /schemas/net/ti,davinci-mdio.yaml# 293 type: object 294 295 "^(pru|rtu|txpru)@[0-9a-f]+$": 296 description: | 297 PRU Node. Each PRUSS has dual PRU cores, each represented as a RemoteProc 298 device through a PRU child node each. Each node can optionally be rendered 299 inactive by using the standard DT string property, "status". The ICSSG IP 300 present on K3 SoCs have additional auxiliary PRU cores with slightly 301 different IP integration. 302 $ref: /schemas/remoteproc/ti,pru-rproc.yaml# 303 type: object 304 305required: 306 - compatible 307 - reg 308 - ranges 309 310additionalProperties: false 311 312# Due to inability of correctly verifying sub-nodes with an @address through 313# the "required" list, the required sub-nodes below are commented out for now. 314 315#required: 316# - memories 317# - interrupt-controller 318# - pru 319 320allOf: 321 - if: 322 properties: 323 compatible: 324 contains: 325 enum: 326 - ti,k2g-pruss 327 - ti,am654-icssg 328 - ti,j721e-icssg 329 - ti,am642-icssg 330 then: 331 required: 332 - power-domains 333 334 - if: 335 properties: 336 compatible: 337 contains: 338 enum: 339 - ti,k2g-pruss 340 then: 341 required: 342 - dma-coherent 343 344examples: 345 - | 346 347 /* Example 1 AM33xx PRU-ICSS */ 348 pruss: pruss@0 { 349 compatible = "ti,am3356-pruss"; 350 reg = <0x0 0x80000>; 351 #address-cells = <1>; 352 #size-cells = <1>; 353 ranges; 354 355 pruss_mem: memories@0 { 356 reg = <0x0 0x2000>, 357 <0x2000 0x2000>, 358 <0x10000 0x3000>; 359 reg-names = "dram0", "dram1", "shrdram2"; 360 }; 361 362 pruss_cfg: cfg@26000 { 363 compatible = "ti,pruss-cfg", "syscon"; 364 #address-cells = <1>; 365 #size-cells = <1>; 366 reg = <0x26000 0x2000>; 367 ranges = <0x00 0x26000 0x2000>; 368 369 clocks { 370 #address-cells = <1>; 371 #size-cells = <0>; 372 373 pruss_iepclk_mux: iepclk-mux@30 { 374 reg = <0x30>; 375 #clock-cells = <0>; 376 clocks = <&l3_gclk>, /* icss_iep */ 377 <&pruss_ocp_gclk>; /* icss_ocp */ 378 }; 379 }; 380 }; 381 382 pruss_mii_rt: mii-rt@32000 { 383 compatible = "ti,pruss-mii", "syscon"; 384 reg = <0x32000 0x58>; 385 }; 386 387 pruss_intc: interrupt-controller@20000 { 388 compatible = "ti,pruss-intc"; 389 reg = <0x20000 0x2000>; 390 interrupt-controller; 391 #interrupt-cells = <3>; 392 interrupts = <20 21 22 23 24 25 26 27>; 393 interrupt-names = "host_intr0", "host_intr1", 394 "host_intr2", "host_intr3", 395 "host_intr4", "host_intr5", 396 "host_intr6", "host_intr7"; 397 }; 398 399 pru0: pru@34000 { 400 compatible = "ti,am3356-pru"; 401 reg = <0x34000 0x2000>, 402 <0x22000 0x400>, 403 <0x22400 0x100>; 404 reg-names = "iram", "control", "debug"; 405 firmware-name = "am335x-pru0-fw"; 406 }; 407 408 pru1: pru@38000 { 409 compatible = "ti,am3356-pru"; 410 reg = <0x38000 0x2000>, 411 <0x24000 0x400>, 412 <0x24400 0x100>; 413 reg-names = "iram", "control", "debug"; 414 firmware-name = "am335x-pru1-fw"; 415 }; 416 417 pruss_mdio: mdio@32400 { 418 compatible = "ti,davinci_mdio"; 419 reg = <0x32400 0x90>; 420 clocks = <&dpll_core_m4_ck>; 421 clock-names = "fck"; 422 bus_freq = <1000000>; 423 #address-cells = <1>; 424 #size-cells = <0>; 425 }; 426 }; 427 428 - | 429 430 /* Example 2 AM43xx PRU-ICSS with PRUSS1 node */ 431 #include <dt-bindings/interrupt-controller/arm-gic.h> 432 pruss1: pruss@0 { 433 compatible = "ti,am4376-pruss1"; 434 reg = <0x0 0x40000>; 435 #address-cells = <1>; 436 #size-cells = <1>; 437 ranges; 438 439 pruss1_mem: memories@0 { 440 reg = <0x0 0x2000>, 441 <0x2000 0x2000>, 442 <0x10000 0x8000>; 443 reg-names = "dram0", "dram1", "shrdram2"; 444 }; 445 446 pruss1_cfg: cfg@26000 { 447 compatible = "ti,pruss-cfg", "syscon"; 448 #address-cells = <1>; 449 #size-cells = <1>; 450 reg = <0x26000 0x2000>; 451 ranges = <0x00 0x26000 0x2000>; 452 453 clocks { 454 #address-cells = <1>; 455 #size-cells = <0>; 456 457 pruss1_iepclk_mux: iepclk-mux@30 { 458 reg = <0x30>; 459 #clock-cells = <0>; 460 clocks = <&sysclk_div>, /* icss_iep */ 461 <&pruss_ocp_gclk>; /* icss_ocp */ 462 }; 463 }; 464 }; 465 466 pruss1_mii_rt: mii-rt@32000 { 467 compatible = "ti,pruss-mii", "syscon"; 468 reg = <0x32000 0x58>; 469 }; 470 471 pruss1_intc: interrupt-controller@20000 { 472 compatible = "ti,pruss-intc"; 473 reg = <0x20000 0x2000>; 474 interrupt-controller; 475 #interrupt-cells = <3>; 476 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 477 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 478 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 479 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 480 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 481 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 482 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 483 interrupt-names = "host_intr0", "host_intr1", 484 "host_intr2", "host_intr3", 485 "host_intr4", 486 "host_intr6", "host_intr7"; 487 ti,irqs-reserved = /bits/ 8 <0x20>; /* BIT(5) */ 488 }; 489 490 pru1_0: pru@34000 { 491 compatible = "ti,am4376-pru"; 492 reg = <0x34000 0x3000>, 493 <0x22000 0x400>, 494 <0x22400 0x100>; 495 reg-names = "iram", "control", "debug"; 496 firmware-name = "am437x-pru1_0-fw"; 497 }; 498 499 pru1_1: pru@38000 { 500 compatible = "ti,am4376-pru"; 501 reg = <0x38000 0x3000>, 502 <0x24000 0x400>, 503 <0x24400 0x100>; 504 reg-names = "iram", "control", "debug"; 505 firmware-name = "am437x-pru1_1-fw"; 506 }; 507 508 pruss1_mdio: mdio@32400 { 509 compatible = "ti,davinci_mdio"; 510 reg = <0x32400 0x90>; 511 clocks = <&dpll_core_m4_ck>; 512 clock-names = "fck"; 513 bus_freq = <1000000>; 514 #address-cells = <1>; 515 #size-cells = <0>; 516 }; 517 }; 518 519... 520