1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/soc/ti/ti,pruss.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: |+ 8 TI Programmable Real-Time Unit and Industrial Communication Subsystem 9 10maintainers: 11 - Suman Anna <s-anna@ti.com> 12 13description: |+ 14 15 The Programmable Real-Time Unit and Industrial Communication Subsystem 16 (PRU-ICSS a.k.a. PRUSS) is present on various TI SoCs such as AM335x, AM437x, 17 Keystone 66AK2G, OMAP-L138/DA850 etc. A PRUSS consists of dual 32-bit RISC 18 cores (Programmable Real-Time Units, or PRUs), shared RAM, data and 19 instruction RAMs, some internal peripheral modules to facilitate industrial 20 communication, and an interrupt controller. 21 22 The programmable nature of the PRUs provide flexibility to implement custom 23 peripheral interfaces, fast real-time responses, or specialized data handling. 24 The common peripheral modules include the following, 25 - an Ethernet MII_RT module with two MII ports 26 - an MDIO port to control external Ethernet PHYs 27 - an Industrial Ethernet Peripheral (IEP) to manage/generate Industrial 28 Ethernet functions 29 - an Enhanced Capture Module (eCAP) 30 - an Industrial Ethernet Timer with 7/9 capture and 16 compare events 31 - a 16550-compatible UART to support PROFIBUS 32 - Enhanced GPIO with async capture and serial support 33 34 A PRU-ICSS subsystem can have up to three shared data memories. A PRU core 35 acts on a primary Data RAM (there are usually 2 Data RAMs) at its address 36 0x0, but also has access to a secondary Data RAM (primary to the other PRU 37 core) at its address 0x2000. A shared Data RAM, if present, can be accessed 38 by both the PRU cores. The Interrupt Controller (INTC) and a CFG module are 39 common to both the PRU cores. Each PRU core also has a private instruction 40 RAM, and specific register spaces for Control and Debug functionalities. 41 42 Various sub-modules within a PRU-ICSS subsystem are represented as individual 43 nodes and are defined using a parent-child hierarchy depending on their 44 integration within the IP and the SoC. These nodes are described in the 45 following sections. 46 47 48 PRU-ICSS Node 49 ============== 50 Each PRU-ICSS instance is represented as its own node with the individual PRU 51 processor cores, the memories node, an INTC node and an MDIO node represented 52 as child nodes within this PRUSS node. This node shall be a child of the 53 corresponding interconnect bus nodes or target-module nodes. 54 55 See ../../mfd/syscon.yaml for generic SysCon binding details. 56 57 58properties: 59 $nodename: 60 pattern: "^(pruss|icssg)@[0-9a-f]+$" 61 62 compatible: 63 enum: 64 - ti,am3356-pruss # for AM335x SoC family 65 - ti,am4376-pruss0 # for AM437x SoC family and PRUSS unit 0 66 - ti,am4376-pruss1 # for AM437x SoC family and PRUSS unit 1 67 - ti,am5728-pruss # for AM57xx SoC family 68 - ti,k2g-pruss # for 66AK2G SoC family 69 - ti,am654-icssg # for K3 AM65x SoC family 70 - ti,j721e-icssg # for K3 J721E SoC family 71 72 reg: 73 maxItems: 1 74 75 "#address-cells": 76 const: 1 77 78 "#size-cells": 79 const: 1 80 81 ranges: 82 maxItems: 1 83 84 dma-ranges: 85 maxItems: 1 86 87 power-domains: 88 description: | 89 This property is as per sci-pm-domain.txt. 90 91patternProperties: 92 93 memories@[a-f0-9]+$: 94 description: | 95 The various Data RAMs within a single PRU-ICSS unit are represented as a 96 single node with the name 'memories'. 97 98 type: object 99 100 properties: 101 reg: 102 minItems: 2 # On AM437x one of two PRUSS units don't contain Shared RAM. 103 maxItems: 3 104 items: 105 - description: Address and size of the Data RAM0. 106 - description: Address and size of the Data RAM1. 107 - description: | 108 Address and size of the Shared Data RAM. Note that on AM437x one 109 of two PRUSS units don't contain Shared RAM, while the second one 110 has it. 111 112 reg-names: 113 minItems: 2 114 maxItems: 3 115 items: 116 - const: dram0 117 - const: dram1 118 - const: shrdram2 119 120 required: 121 - reg 122 - reg-names 123 124 additionalProperties: false 125 126 cfg@[a-f0-9]+$: 127 description: | 128 PRU-ICSS configuration space. CFG sub-module represented as a SysCon. 129 130 type: object 131 132 properties: 133 compatible: 134 items: 135 - const: ti,pruss-cfg 136 - const: syscon 137 138 "#address-cells": 139 const: 1 140 141 "#size-cells": 142 const: 1 143 144 reg: 145 maxItems: 1 146 147 ranges: 148 maxItems: 1 149 150 clocks: 151 type: object 152 153 properties: 154 "#address-cells": 155 const: 1 156 157 "#size-cells": 158 const: 0 159 160 patternProperties: 161 coreclk-mux@[a-f0-9]+$: 162 description: | 163 This is applicable only for ICSSG (K3 SoCs). The ICSSG modules 164 core clock can be set to one of the 2 sources: ICSSG_CORE_CLK or 165 ICSSG_ICLK. This node models this clock mux and should have the 166 name "coreclk-mux". 167 168 type: object 169 170 properties: 171 '#clock-cells': 172 const: 0 173 174 clocks: 175 items: 176 - description: ICSSG_CORE Clock 177 - description: ICSSG_ICLK Clock 178 179 assigned-clocks: 180 maxItems: 1 181 182 assigned-clock-parents: 183 maxItems: 1 184 description: | 185 Standard assigned-clocks-parents definition used for selecting 186 mux parent (one of the mux input). 187 188 reg: 189 maxItems: 1 190 191 required: 192 - clocks 193 194 additionalProperties: false 195 196 iepclk-mux@[a-f0-9]+$: 197 description: | 198 The IEP module can get its clock from 2 sources: ICSSG_IEP_CLK or 199 CORE_CLK (OCP_CLK in older SoCs). This node models this clock 200 mux and should have the name "iepclk-mux". 201 202 type: object 203 204 properties: 205 '#clock-cells': 206 const: 0 207 208 clocks: 209 items: 210 - description: ICSSG_IEP Clock 211 - description: Core Clock (OCP Clock in older SoCs) 212 213 assigned-clocks: 214 maxItems: 1 215 216 assigned-clock-parents: 217 maxItems: 1 218 description: | 219 Standard assigned-clocks-parents definition used for selecting 220 mux parent (one of the mux input). 221 222 reg: 223 maxItems: 1 224 225 required: 226 - clocks 227 228 additionalProperties: false 229 230 additionalProperties: false 231 232 iep@[a-f0-9]+$: 233 description: | 234 Industrial Ethernet Peripheral to manage/generate Industrial Ethernet 235 functions such as time stamping. Each PRUSS has either 1 IEP (on AM335x, 236 AM437x, AM57xx & 66AK2G SoCs) or 2 IEPs (on K3 AM65x & J721E SoCs ). IEP 237 is used for creating PTP clocks and generating PPS signals. 238 239 type: object 240 241 mii-rt@[a-f0-9]+$: 242 description: | 243 Real-Time Ethernet to support multiple industrial communication protocols. 244 MII-RT sub-module represented as a SysCon. 245 246 type: object 247 248 properties: 249 compatible: 250 items: 251 - const: ti,pruss-mii 252 - const: syscon 253 254 reg: 255 maxItems: 1 256 257 additionalProperties: false 258 259 mii-g-rt@[a-f0-9]+$: 260 description: | 261 The Real-time Media Independent Interface to support multiple industrial 262 communication protocols (G stands for Gigabit). MII-G-RT sub-module 263 represented as a SysCon. 264 265 type: object 266 267 properties: 268 compatible: 269 items: 270 - const: ti,pruss-mii-g 271 - const: syscon 272 273 reg: 274 maxItems: 1 275 276 additionalProperties: false 277 278 interrupt-controller@[a-f0-9]+$: 279 description: | 280 PRUSS INTC Node. Each PRUSS has a single interrupt controller instance 281 that is common to all the PRU cores. This should be represented as an 282 interrupt-controller node. 283 284 allOf: 285 - $ref: /schemas/interrupt-controller/ti,pruss-intc.yaml# 286 287 type: object 288 289 mdio@[a-f0-9]+$: 290 description: | 291 MDIO Node. Each PRUSS has an MDIO module that can be used to control 292 external PHYs. The MDIO module used within the PRU-ICSS is an instance of 293 the MDIO Controller used in TI Davinci SoCs. 294 295 allOf: 296 - $ref: /schemas/net/ti,davinci-mdio.yaml# 297 298 type: object 299 300 "^(pru|rtu|txpru)@[0-9a-f]+$": 301 description: | 302 PRU Node. Each PRUSS has dual PRU cores, each represented as a RemoteProc 303 device through a PRU child node each. Each node can optionally be rendered 304 inactive by using the standard DT string property, "status". The ICSSG IP 305 present on K3 SoCs have additional auxiliary PRU cores with slightly 306 different IP integration. 307 308 allOf: 309 - $ref: /schemas/remoteproc/ti,pru-rproc.yaml# 310 311 type: object 312 313required: 314 - compatible 315 - reg 316 - ranges 317 318additionalProperties: false 319 320# Due to inability of correctly verifying sub-nodes with an @address through 321# the "required" list, the required sub-nodes below are commented out for now. 322 323#required: 324# - memories 325# - interrupt-controller 326# - pru 327 328if: 329 properties: 330 compatible: 331 contains: 332 enum: 333 - ti,k2g-pruss 334 - ti,am654-icssg 335 - ti,j721e-icssg 336then: 337 required: 338 - power-domains 339 340examples: 341 - | 342 343 /* Example 1 AM33xx PRU-ICSS */ 344 pruss: pruss@0 { 345 compatible = "ti,am3356-pruss"; 346 reg = <0x0 0x80000>; 347 #address-cells = <1>; 348 #size-cells = <1>; 349 ranges; 350 351 pruss_mem: memories@0 { 352 reg = <0x0 0x2000>, 353 <0x2000 0x2000>, 354 <0x10000 0x3000>; 355 reg-names = "dram0", "dram1", "shrdram2"; 356 }; 357 358 pruss_cfg: cfg@26000 { 359 compatible = "ti,pruss-cfg", "syscon"; 360 #address-cells = <1>; 361 #size-cells = <1>; 362 reg = <0x26000 0x2000>; 363 ranges = <0x00 0x26000 0x2000>; 364 365 clocks { 366 #address-cells = <1>; 367 #size-cells = <0>; 368 369 pruss_iepclk_mux: iepclk-mux@30 { 370 reg = <0x30>; 371 #clock-cells = <0>; 372 clocks = <&l3_gclk>, /* icss_iep */ 373 <&pruss_ocp_gclk>; /* icss_ocp */ 374 }; 375 }; 376 }; 377 378 pruss_mii_rt: mii-rt@32000 { 379 compatible = "ti,pruss-mii", "syscon"; 380 reg = <0x32000 0x58>; 381 }; 382 383 pruss_intc: interrupt-controller@20000 { 384 compatible = "ti,pruss-intc"; 385 reg = <0x20000 0x2000>; 386 interrupt-controller; 387 #interrupt-cells = <3>; 388 interrupts = <20 21 22 23 24 25 26 27>; 389 interrupt-names = "host_intr0", "host_intr1", 390 "host_intr2", "host_intr3", 391 "host_intr4", "host_intr5", 392 "host_intr6", "host_intr7"; 393 }; 394 395 pru0: pru@34000 { 396 compatible = "ti,am3356-pru"; 397 reg = <0x34000 0x2000>, 398 <0x22000 0x400>, 399 <0x22400 0x100>; 400 reg-names = "iram", "control", "debug"; 401 firmware-name = "am335x-pru0-fw"; 402 }; 403 404 pru1: pru@38000 { 405 compatible = "ti,am3356-pru"; 406 reg = <0x38000 0x2000>, 407 <0x24000 0x400>, 408 <0x24400 0x100>; 409 reg-names = "iram", "control", "debug"; 410 firmware-name = "am335x-pru1-fw"; 411 }; 412 413 pruss_mdio: mdio@32400 { 414 compatible = "ti,davinci_mdio"; 415 reg = <0x32400 0x90>; 416 clocks = <&dpll_core_m4_ck>; 417 clock-names = "fck"; 418 bus_freq = <1000000>; 419 #address-cells = <1>; 420 #size-cells = <0>; 421 }; 422 }; 423 424 - | 425 426 /* Example 2 AM43xx PRU-ICSS with PRUSS1 node */ 427 #include <dt-bindings/interrupt-controller/arm-gic.h> 428 pruss1: pruss@0 { 429 compatible = "ti,am4376-pruss1"; 430 reg = <0x0 0x40000>; 431 #address-cells = <1>; 432 #size-cells = <1>; 433 ranges; 434 435 pruss1_mem: memories@0 { 436 reg = <0x0 0x2000>, 437 <0x2000 0x2000>, 438 <0x10000 0x8000>; 439 reg-names = "dram0", "dram1", "shrdram2"; 440 }; 441 442 pruss1_cfg: cfg@26000 { 443 compatible = "ti,pruss-cfg", "syscon"; 444 #address-cells = <1>; 445 #size-cells = <1>; 446 reg = <0x26000 0x2000>; 447 ranges = <0x00 0x26000 0x2000>; 448 449 clocks { 450 #address-cells = <1>; 451 #size-cells = <0>; 452 453 pruss1_iepclk_mux: iepclk-mux@30 { 454 reg = <0x30>; 455 #clock-cells = <0>; 456 clocks = <&sysclk_div>, /* icss_iep */ 457 <&pruss_ocp_gclk>; /* icss_ocp */ 458 }; 459 }; 460 }; 461 462 pruss1_mii_rt: mii-rt@32000 { 463 compatible = "ti,pruss-mii", "syscon"; 464 reg = <0x32000 0x58>; 465 }; 466 467 pruss1_intc: interrupt-controller@20000 { 468 compatible = "ti,pruss-intc"; 469 reg = <0x20000 0x2000>; 470 interrupt-controller; 471 #interrupt-cells = <3>; 472 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 473 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 474 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 475 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 476 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 477 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 478 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 479 interrupt-names = "host_intr0", "host_intr1", 480 "host_intr2", "host_intr3", 481 "host_intr4", 482 "host_intr6", "host_intr7"; 483 ti,irqs-reserved = /bits/ 8 <0x20>; /* BIT(5) */ 484 }; 485 486 pru1_0: pru@34000 { 487 compatible = "ti,am4376-pru"; 488 reg = <0x34000 0x3000>, 489 <0x22000 0x400>, 490 <0x22400 0x100>; 491 reg-names = "iram", "control", "debug"; 492 firmware-name = "am437x-pru1_0-fw"; 493 }; 494 495 pru1_1: pru@38000 { 496 compatible = "ti,am4376-pru"; 497 reg = <0x38000 0x3000>, 498 <0x24000 0x400>, 499 <0x24400 0x100>; 500 reg-names = "iram", "control", "debug"; 501 firmware-name = "am437x-pru1_1-fw"; 502 }; 503 504 pruss1_mdio: mdio@32400 { 505 compatible = "ti,davinci_mdio"; 506 reg = <0x32400 0x90>; 507 clocks = <&dpll_core_m4_ck>; 508 clock-names = "fck"; 509 bus_freq = <1000000>; 510 #address-cells = <1>; 511 #size-cells = <0>; 512 }; 513 }; 514 515... 516